Analog IC Design Engineer

MANPOWER STAFFING SERVICES (SINGAPORE) PTE LTD; Singapore; On-site; SGD 90,000 - 120,000; Full time

Job summary

MANPOWER STAFFING SERVICES (SINGAPORE) PTE LTD is seeking an experienced analog IC design engineer to drive PMU blocks from spec to silicon, collaborating with layout and test teams.

You will model, simulate, and verify DCDC/LDO/PLL/ADC blocks, ensure post-layout RC extraction across PVT, and support silicon characterization and reliability.

Applicants hold a Master’s in EEE; hands-on tape-out experience and strong knowledge of analog EDA tools are required.

Qualifications

• Master or higher degree in Electrical/Electronic Engineering.
• Design experience in PMU blocks (DCDC, LDO, BG, POR) is required.
• Experience with ADC or PLL is an added advantage.
• Experience with multiple full tape-outs and silicon IPs is beneficial.
• Strong working knowledge of analog EDA tools is expected.
• Demonstrates teamwork and collaboration skills.

Responsibilities

• Develop analog/mixed-signal circuits from spec to prototype.
• Perform SPICE modeling and PMU simulations across PVT to meet specs.
• Modify and improve existing analog IP for performance gains.
• Coordinate with layout engineers to align with process nodes.
• Handle post-layout RC extraction and verification for all corners.
• Build test requirements for silicon characterization and testing.
• Address IP reliability, ESD, and robustness concerns.

Skills

Analog/Mixed Signal design

PMU (DCDC, LDO, BG, POR)

ADC/PLL experience

Tape-out / silicon IP experience

Analog EDA tools

Team player

Education

Master / Degree Electrical/Electronic Engineering

Tools

Analog EDA tools

Job description

Job Description

1. Development of Analog/Mixed Signal circuits from Specification to prototypes
2. Perform Analog Spice behavior modelling and simulation of Power Management Unit like DCDC, LDO , PLL , ADC across PVT to meet specification.
3. Modify and improve existing Analog IP to improve performance to meet specification
4. Work with layout engineers to complete layout align with process nodes requirement
5. Responsible for all post layout circuits with RC extraction and simulation to meet all PVT corners
6. Responsible for building test requirement for silicon characterization and functional testing
7. Able to handle all IP related reliability, ESD and robustness

Job Requirements

• Master / Degree Electrical/Electronic Engineering
• Design experience in PMU like DCDC , LDO , smaller build blocks of analog circuits, BG , POR is a must
• Experience in ADC or PLL is an added advantage
• Experience with a few full tape-out and silicon IPs will be an added advantage
• Good working knowledge of Analog EDA tools
• Team player