[2026 Campus] Engineer / Senior Engineer (Design Verification)

聯發科技; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

A leading technology company in Singapore seeks an experienced design verification engineer to work on innovative projects involving WiFi, 5G, and AI. The ideal candidate will have a Bachelor's or Master's degree and at least 2 years of experience in SOC verification, along with strong skills in SystemVerilog and UVM. Join a diverse team that promotes professional growth and learning opportunities.

Qualifications

• Minimum 2 years of relevant experience in IC/ASIC design verification.
• Experience with SOC, Ethernet, PCIe, DDR, USB, ARM CPU verification.
• Strong debugging skills with SystemVerilog/UVM.

Responsibilities

• Perform Module/IP/SOC design verification.
• Develop and implement test plans and verification environments.
• Conduct low power and formal verification.

Skills

Module/IP/SOC design verification

Test plan development and review

Verification environment/testbench development

Functional and functional/code coverage closure

Debugging with UVM, SystemVerilog, Verilog

Low Power verification

UNIX scripting with Python

Education

Bachelor's Degree in EEE/Computer/IC design

Master's Degree in EEE/Computer/IC design

Tools

SystemVerilog

UVM

Synopsys

Cadence

Mentor Simulator

Job description

Overview

Date: 1 day ago Area: Tuas, West Contract: Full time

What you will do

• Module/IP/SOC design verification.
• Develop and review test plans.
• Develop verification environment/testbench at Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization-based coverage-driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC.
• Low Power verification.
• Formal verification.
• Verification automation flow.

What you will bring

• Bachelor\'s Degree (with min. 2 years of relevant experience) / Master\'s Degree in EEE/Computer/IC design.
• IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on SystemVerilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Python, Perl, makefile Cshell.
• Quick to learn new technology.

Location

One North, Singapore

About the Team

ASIC DV Team focus on developing full and advanced verification methodology IP/SOC. You will have chance to work on challenging projects that attractive and be immersed in leading tech e.g.: WiFi, 5G, AR/VR, AI, Cloud Networking. A comprehensive program for professional development / career growth will be provided to the new joiner and he/she will have chance to learn from the best expert in this area. In MediaTek, we promote diversity and inclusiveness. Passionate talents who love new challenges and keen on learning new technologies, do send us your cv our way today and join our multicultural team that consists of talents from all over the world!