Senior ASIC Synthesis & Timing Engineer

Ericsson GmbH; Skåne län; On-site; SEK 900,000 - 1,300,000; Full time

Job summary

Ericsson is seeking an experienced ASIC Synthesis Engineer in Sweden to drive backend tasks such as synthesis, constraints, and timing closure. You will run STA, sign-off timing, and optimize across timing, area, and power using Synopsys tools, while scripting in Python, TCL, and Linux to automate workflows.

You will collaborate with cross-functional teams on low-power design techniques and physical implementation strategies, contributing to next-generation 5G/6G projects.

Qualifications

• 5+ years of ASIC backend development and tape-outs.
• Strong expertise with Synopsys tools for timing, area, and power closure.
• Proficient in scripting (Python, TCL, Linux shell) to automate flows.

Responsibilities

• Engage in synthesis, constraints development, equivalence checking, and P&R.
• Run STA, timing sign-off, and optimize timing/area/power with Synopsys tools.
• Develop scripts to automate processes and improve project efficiency.
• Collaborate with cross-functional teams on low-power design and floor planning.

Skills

Backend development

Synthesis

STA

Power optimization

Scripting

UNIX/Linux

Low-power design

RTL2GDS flows

Tools

Design Compiler

Fusion Compiler

PrimeTime

ICC2/Innovus

Formality/LEC

Git

SpyGlass

ClearCase

Job description

Ericsson is seeking an experienced ASIC Synthesis Engineer in Sweden to drive backend tasks such as synthesis, constraints, and timing closure. You will run STA, sign-off timing, and optimize across timing, area, and power using Synopsys tools, while scripting in Python, TCL, and Linux to automate workflows.

You will collaborate with cross-functional teams on low-power design techniques and physical implementation strategies, contributing to next-generation 5G/6G projects.