Senior ASIC Synthesis Engineer – Low-Power & 5G/6G

Ericsson; Lunds kommun; On-site; SEK 900,000 - 1,300,000; Full time

Job summary

Ericsson in Sweden is seeking an experienced ASIC Synthesis Engineer to shape the next generation of 5G/6G technology. You will contribute to the final backend stage of chip design, focusing on synthesis, timing, and power optimization for digital ASICs used in mobile networks.

Join a Lean, Agile team that values collaboration, continuous improvement, and hands-on scripting to automate flows. You’ll work with state-of-the-art EDA tools and be part of a global telecom leader driving innovation.

Qualifications

• Expertise in backend development, specialising in synthesis, STA, and power optimisation in semiconductors.
• 5+ years of development experience through multiple ASIC tape-outs.
• Hands-on Knowledge of EDA tools for timing and power closure.
• Proficiency in scripting languages to automate workflows.
• UNIX/Linux environment experience.
• Experience with low-power design using UPF and RTL2GDS flows.
• Ability to craft timing constraints for complex designs.
• Collaborative mindset and strong communication.

Responsibilities

• Engage in all backend development tasks, including synthesis, constraints development, equivalence checking, and place-and-route to deliver high-quality digital ASICs.
• Run Static Timing Analysis, timing sign-off, and optimize timing/area/power using Synopsys tools (Design Compiler, PrimeTime, ICC2/FC/Innovus).
• Work extensively with EDA tools and develop scripts (Python, TCL, Linux Shell) to automate processes and enhance project efficiency.
• Drive innovations in low-power design using UPF and provide input on physical implementation and floor planning.
• Collaborate with cross-functional teams in a supportive, knowledge-sharing environment, ensuring seamless integration and execution.

Job description

Ericsson in Sweden is seeking an experienced ASIC Synthesis Engineer to shape the next generation of 5G/6G technology. You will contribute to the final backend stage of chip design, focusing on synthesis, timing, and power optimization for digital ASICs used in mobile networks.

Join a Lean, Agile team that values collaboration, continuous improvement, and hands-on scripting to automate flows. You’ll work with state-of-the-art EDA tools and be part of a global telecom leader driving innovation.