RISC-V Simics Architecture Modeler

UST; Województwo pomorskie; On-site; PLN 150,000 - 190,000; Full time

Job summary

UST is seeking a mid-senior to senior Simics Developer to support the development and implementation of a new architecture model based on RISC-V cores. The role emphasizes hands-on Simics development, architecture modeling, and system-level simulation.

You will collaborate with engineering teams to define, implement, and validate architectural solutions, develop and maintain simulation environments, and produce clear technical documentation.

Qualifications

• Hands-on Simics development experience.
• Strong model-based architecture and system-level simulation skills.
• Solid understanding of RISC-V cores and architecture.

Responsibilities

• Design, develop, and implement architecture models using Simics.
• Support modeling and simulation activities involving RISC-V processors and cores.
• Collaborate with technical teams to define, implement, and validate architectural solutions.
• Develop and maintain simulation environments required for architecture development and testing.
• Investigate, troubleshoot, and resolve issues identified during model implementation and validation.
• Contribute to architecture verification efforts and ensure model accuracy and performance.
• Create and maintain technical documentation related to model development and implementation.

Skills

Simics Development

Architecture Modeling

RISC-V Architecture

System Simulation

Debugging & Troubleshooting

Performance Analysis

Technical Documentation

Problem Solving

Tools

C/C++

Python

Job description

UST is seeking a mid-senior to senior Simics Developer to support the development and implementation of a new architecture model based on RISC-V cores. The role emphasizes hands-on Simics development, architecture modeling, and system-level simulation.

You will collaborate with engineering teams to define, implement, and validate architectural solutions, develop and maintain simulation environments, and produce clear technical documentation.