Principal RTL Design Engineer for SoC Innovation

Cadence; Katowice; On-site; PLN 519,000 - 778,000; Full time

Benefits offered by this job

Travel: <10%

Job summary

Cadence is seeking a Principal Digital Design Engineer to join the Performance Solutions Group across Munich, Cork, Katowice, and Edinburgh. You will drive development of high-performance RTL for advanced SoCs and silicon platforms, contributing across architecture, RTL, verification and physical implementation.

You will collaborate with architects and senior engineers to meet performance and power targets, while delivering robust, synthesizable RTL and leading design methodology improvements.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 10+ years of relevant RTL/ASIC design experience.
• Proficiency in Verilog or SystemVerilog.
• Understanding of digital logic design and synchronous design principles.
• Experience developing synthesizable RTL for ASIC or FPGA implementations.
• Familiarity with simulation and RTL debugging.
• Understanding of common SoC interfaces and protocols.
• Basic understanding of synthesis, timing, and physical implementation considerations.
• Ability to analyze complex technical problems and develop practical solutions.
• Strong written and verbal communication skills.
• Ability to work effectively within a multidisciplinary engineering team.
• Ability to communicate effectively to customers

Responsibilities

• Design, implement, and integrate high-quality synthesizable RTL using SystemVerilog.
• Translate architectural specifications into robust, efficient microarchitectures and RTL implementations.
• Work with architects and senior engineers to understand functional and performance requirements.
• Develop RTL that meets requirements for performance, power, area, and functionality.
• Participate in RTL design reviews and contribute to design methodology and coding standards.
• Develop and maintain unit-level and block-level test environments in collaboration with verification engineers.
• Debug functional issues using simulation, waveform analysis, assertions, and other verification tools.
• Work with verification teams to identify, reproduce, and resolve RTL design issues.
• Collaborate with physical design engineers to understand and address timing, area, power, and implementation constraints.
• Support synthesis, timing analysis, linting, CDC analysis, and other front-end quality checks.
• Contribute to integration of internally developed and third-party IP.
• Help investigate and resolve issues encountered during integration and downstream implementation.
• Document design decisions, interfaces, microarchitecture, implementation details and reviews within the PSG Quality Management System (QMS)
• Contribute to continuous improvement of RTL methodologies, automation, and development flows.
• Work alongside senior engineers to develop solutions to challenging customer and internal silicon problems.

Skills

SystemVerilog RTL

RTL/ASIC design

SoC architectures

Verilog/SystemVerilog

Team collaboration

Education

Bachelor's or Master's in EE/CE

Tools

Cadence toolset

RTL debugging tools

Job description

Cadence is seeking a Principal Digital Design Engineer to join the Performance Solutions Group across Munich, Cork, Katowice, and Edinburgh. You will drive development of high-performance RTL for advanced SoCs and silicon platforms, contributing across architecture, RTL, verification and physical implementation.

You will collaborate with architects and senior engineers to meet performance and power targets, while delivering robust, synthesizable RTL and leading design methodology improvements.