Senior RTL SoC Designer - Hybrid Role

Capgemini Engineering; Katowice; Hybrid; PLN 180,000 - 260,000; Full time

Benefits offered by this job

Medical care with Medicover

Private life insurance

Sports card

Hybrid work model

Job summary

Capgemini Engineering is seeking a senior Digital Design expert to join our semiconductor-focused team in Poland. You will lead the development of functional specifications and design high-performance digital blocks for next-generation SoCs.

Ideal candidates bring 7+ years in digital design, strong Verilog/VHDL skills, SystemVerilog familiarity, and hands-on experience with leading EDA tools. Hybrid work arrangement and collaboration with cross-functional teams are offered.

Qualifications

• 7+ years of hands-on experience in digital design.
• Strong knowledge of Verilog and/or VHDL.
• Familiarity with SystemVerilog is a plus.
• Experience with Cadence Genus, Synopsys Design Compiler (DC), or Fusion Compiler is a plus.
• Proven experience in RTL design, uArch development, and functional specs.
• Deep understanding of linting tools, CDC methodologies, and debugging flows.
• Familiarity with synthesis tools and SoC design is a strong plus.
• Excellent communication and collaboration skills.

Responsibilities

• Lead Functional Specification Development for advanced digital systems
• Design and implement Microarchitecture (uArch) for high-performance blocks
• Perform RTL Debugging, ensuring design correctness and efficiency
• Run and analyze Lint Checks and CDC (Clock Domain Crossing) Checks
• Collaborate with verification, physical design, and architecture teams
• Bonus: Contribute to Front-End Synthesis and optimization
• Nice to have: SoC-level integration and design experience
• Nice to have: Power optimization techniques for energy-efficient designs

Skills

Digital design

RTL design

uArch development

Verilog/VHDL

SystemVerilog

Communication skills

Tools

Cadence Genus

Synopsys Design Compiler (DC)

Fusion Compiler

Job description

Capgemini Engineering is seeking a senior Digital Design expert to join our semiconductor-focused team in Poland. You will lead the development of functional specifications and design high-performance digital blocks for next-generation SoCs.

Ideal candidates bring 7+ years in digital design, strong Verilog/VHDL skills, SystemVerilog familiarity, and hands-on experience with leading EDA tools. Hybrid work arrangement and collaboration with cross-functional teams are offered.