Principal ASIC Verification Engineer – SoC & AI-Driven

Blue Origin; Kraków; On-site; PLN 260,000 - 480,000; Full time

Job summary

Blue Origin in Kraków is seeking a Principal Verification Engineer to lead chip and subsystem verification for the ASIC & Networking program. You will define verification strategy, drive coverage, and guide simulation and formal methods while collaborating with global teams.

We value a strong background in SystemVerilog, UVM, and leadership of taped-out silicon projects. Willingness to travel up to 10% is expected as part of this role.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum ten years of professional experience in ASIC or SoC functional verification.
• Hands-on SystemVerilog and UVM testbench development, plus metric driven verification.
• Experience as verification technical lead on at least one taped out silicon program.
• Willingness to travel up to 10 percent to other team locations.

Responsibilities

• Lead verification for chip level and complex subsystems through sign-off with global teams.
• Own verification strategy, test plans, and measurable coverage goals across subsystems and SoC.
• Identify verification gaps and implement methodology changes across the organization.
• Serve as subject area expert, setting technical direction and resolving issues.
• Architect reusable verification environments and infrastructure across IP, subsystem, and SoC levels.
• Drive regression health, coverage closure, and sign-off readiness across simulation and formal results.
• Review testbench architecture and mentor engineers in verification methodology.

Skills

SystemVerilog

UVM

Metric-driven verification

Verification leadership

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

SystemVerilog/UVM toolchain

Job description

Blue Origin in Kraków is seeking a Principal Verification Engineer to lead chip and subsystem verification for the ASIC & Networking program. You will define verification strategy, drive coverage, and guide simulation and formal methods while collaborating with global teams.

We value a strong background in SystemVerilog, UVM, and leadership of taped-out silicon projects. Willingness to travel up to 10% is expected as part of this role.