PD Partition Lead (Physical Design, Semiconductors)

Capgemini Engineering; Lublin; Hybrid; PLN 240,000 - 360,000; Full time

Benefits offered by this job

Medicover medical care

Private life insurance

Sports card

Hybrid working model

Job summary

Capgemini Polska is seeking a PD Partitioning Lead to drive physical design activities for advanced nodes. You will lead floorplanning, partitioning, power mesh, clock tree planning, and timing closure on challenging projects, with potential to mentor other PD engineers.

Join a globally connected Capgemini team delivering cutting-edge engineering services, with a hybrid work model, strong training, and wellbeing programs.

Qualifications

• Good knowledge of synthesis flow, insertDFT scan/coverage and optimization.
• Excellent floorplan, power plan, CTS, place, route, and timing closure skills;
• Proficiency using Perl/TCL/Python scripting and Makefile;
• Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill;
• Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;
• Experience with sign-off tape-out closure work;
• Partitioning experience is a plus;
• Experience in leading/tech leading small teams will be a plus.

Responsibilities

• Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below).
• In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route.
• Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing).
• In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes.
• Be part of the overall Low Power solution development and implementation.
• Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level).
• Complete multiple design cycles of high complexity with little supervision.
• Possiblity to lead other PD Engineers.

Skills

Synthesis flow

DFT coverage

Floorplanning

Power mesh

Clock tree

Timing closure

Scripting

Tape-out sign-off

Team leadership

EM/IR checks

Tools

Perl

TCL

Python

Makefile

Job description

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s mostinnovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as theyprovide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days arethe same.
Long Description
Are you in search for a new challenge? We are looking for Physical Design expert with experience in partitioning who dreams about becoming a Lead or Tech Lead for new, exciting projects!
Take the opportunity and join us as a

PD Partitioning Lead!

YOUR TASKS

• Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);
• In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;
• Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);
• In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;
• Be part of the overall Low Power solution development and implementation;
• Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level);
• Complete multiple design cycles of high complexity with little supervision.
• Possiblity to lead other PD Engineers.

YOUR PROFILE

• Good knowledge of synthesis flow, insertDFT scan/coverage and optimization;
• Excellent floorplan, power plan, CTS, place, route, and timing closure skills;
• Proficiency using Perl/TCL/Python scripting and Makefile;
• Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill;
• Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;
• Experience with sign-off tape-out closure work;
• Partitioning experience is a plus;
• Experience in leading/tech leading small teams will be a plus.

What You'll Love About Working Here

• Well-being culture: medical care with Medicover, private life insurance, and sports card. But we went one step further by creating our own Capgemini Helpline offering therapeutical support if needed and the educational podcast 'Let's talk about wellbeing' which you can listen to on Spotify.
• Access to over 70 training tracks with certification opportunities (e.g., GenAI, Architects, Google) on our NEXT platform. Dive into a world of knowledge with free access to Education First languages platform, TED Talks and Udemy Business materials and trainings.
• Continuous feedback and ongoing performance discussions thanks to our performance management tool GetSuccess supported by a transparent performance management policy.
• Enjoy hybrid working model that fits your life - after completing onboarding, connect work from a modern office with ergonomic work from home, thanks to home office package (including laptop, monitor, and chair).

GET TO KNOW US

Capgemini is committed to diversity and inclusion, ensuring fairness in all employment practices. We evaluate individuals based on qualifications and performance, not personal characteristics, striving to create a workplace where everyone can succeed and feel valued.

Do you want to get to know us better? Check our Instagram — @capgeminipl or visit our Facebook profile — Capgemini Polska. You can also find us on YouTube.

About Capgemini

Capgemini is an AI-powered global business and technology transformation partner, delivering tangible business value. We imagine the future of organizations and make it real with AI, technology and people. With our strong heritage of nearly 60 years, we are a responsible and diverse group of over 420,000 team members in more than 50 countries. We deliver end-to-end services and solutions with our deep industry expertise and strong partner ecosystem, leveraging our capabilities across strategy, technology, design, engineering and business operations. The Group reported 2025 global revenues of €22.5 billion.