PD Partitioning Lead — Next‑Gen Chip Physical Design

Capgemini Engineering; Lublin; Hybrid; PLN 240,000 - 360,000; Full time

Benefits offered by this job

Medicover medical care

Private life insurance

Sports card

Hybrid working model

Job summary

Capgemini Polska is seeking a PD Partitioning Lead to drive physical design activities for advanced nodes. You will lead floorplanning, partitioning, power mesh, clock tree planning, and timing closure on challenging projects, with potential to mentor other PD engineers.

Join a globally connected Capgemini team delivering cutting-edge engineering services, with a hybrid work model, strong training, and wellbeing programs.

Qualifications

• Good knowledge of synthesis flow, insertDFT scan/coverage and optimization.
• Excellent floorplan, power plan, CTS, place, route, and timing closure skills;
• Proficiency using Perl/TCL/Python scripting and Makefile;
• Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill;
• Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills;
• Experience with sign-off tape-out closure work;
• Partitioning experience is a plus;
• Experience in leading/tech leading small teams will be a plus.

Responsibilities

• Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below).
• In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route.
• Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing).
• In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes.
• Be part of the overall Low Power solution development and implementation.
• Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level).
• Complete multiple design cycles of high complexity with little supervision.
• Possiblity to lead other PD Engineers.

Skills

Synthesis flow

DFT coverage

Floorplanning

Power mesh

Clock tree

Timing closure

Scripting

Tape-out sign-off

Team leadership

EM/IR checks

Tools

Perl

TCL

Python

Makefile

Job description

Capgemini Polska is seeking a PD Partitioning Lead to drive physical design activities for advanced nodes. You will lead floorplanning, partitioning, power mesh, clock tree planning, and timing closure on challenging projects, with potential to mentor other PD engineers.

Join a globally connected Capgemini team delivering cutting-edge engineering services, with a hybrid work model, strong training, and wellbeing programs.