DFT Lead, Semiconductors — Test & IC Reliability

Capgemini Engineering; Katowice; Hybrid; PLN 120,000 - 180,000; Full time

Benefits offered by this job

Medical care

Private insurance

Sports card

Wellbeing helpline

Training tracks and courses

Hybrid work model

Home office package

Job summary

Capgemini Engineering, a world leader in engineering services, seeks a DFT Lead to join our digital design teams in Poland. You will drive DFT/integration across advanced process nodes, collaborating with RTL, timing, and verification engineers to ensure robust test coverage and scalable DFT solutions.

Ideal candidates have 6+ years of hands-on DFT with large SOCs, strong JTAG/ATPG knowledge, and experience with major eda toolchains.

Qualifications

• 6+ years of hands-on experience with DFT and test flows for large SOCs.
• Strong knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500, MBIST/LBIST.

Responsibilities

• DFT implementation inline with existing test methodology for advanced process nodes.
• Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST.
• Collaborate with physical design team to resolve timing constraints/issues.
• Verify DFT circuitry and interface with IPs, debug timing simulations.
• Improve DFT KPIs: test coverage and pattern efficiency.
• Hierarchical retargeting.
• Silicon bring-up, diagnosis and support for physical failure analysis.
• Opportunity to lead a multilocational DFT team.

Skills

DFT

Test flows

JTAG

ATPG

MBIST/LBIST

RTL simulation

Python scripting

Perl scripting

Problem solving

Tools

Synopsys DFT Compiler

Tetramax

VCS

Tessent

Modus/Encounter

Job description

Capgemini Engineering, a world leader in engineering services, seeks a DFT Lead to join our digital design teams in Poland. You will drive DFT/integration across advanced process nodes, collaborating with RTL, timing, and verification engineers to ensure robust test coverage and scalable DFT solutions.

Ideal candidates have 6+ years of hands-on DFT with large SOCs, strong JTAG/ATPG knowledge, and experience with major eda toolchains.