Analog Layout- Sr. Staff Engineer

Axiro Semiconductor Pvt Ltd; Hinoba-an; On-site; PHP 2,322,000 - 3,648,000; Full time

Job summary

Axiro Semiconductor Pvt Ltd., a Bengaluru-based fabless semiconductor design company, seeks a highly experienced Custom IC Layout Lead to oversee analog/mixed-signal layouts and guide a team of junior engineers. You will drive tapeouts across multiple process technologies and collaborate with circuits, verification, and packaging teams.

The role requires 12–15 years of hands-on layout experience, leadership, and proficiency with Cadence/Calibre.

Qualifications

• 12–15 years in RFIC/MMIC/analog/mixed-signal/custom layout across multiple process techs.
• Experience managing multiple concurrent projects and mentoring juniors.
• Proficient with Cadence and Calibre in Linux; scripting in SKILL and Perl desirable.

Responsibilities

• Execute full custom layout of analog/mixed-signal blocks (e.g., ADCs, DACs, PLLs, LDOs).
• Lead and mentor a team of junior layout engineers and provide technical guidance.
• Plan and manage layout execution across multiple projects to meet tapeout deadlines.
• Drive layout strategy and technology qualification across multiple process nodes and technologies.
• Collaborate with design engineers to optimize layout for performance, area and reliability.
• Perform layout verification (DRC, LVS, parasitic extraction).
• Interface with packaging and assembly teams to ensure manufacturing rules adherence.
• Coordinate wafer step plan with design and foundry teams.

Skills

RFIC/MMIC layout

Project leadership

Analog/mixed-signal design

Process technologies

Cadence/Calibre

Scripting (SKILL/Perl)

Design for manufacturability

Cross-functional coordination

Problem solving

Tools

Cadence

Calibre

Job description

Axiro Semiconductor is a fabless semiconductor design company headquartered in Bengaluru, driving innovation in RF, wireless infrastructure, satellite communication (Satcom), and high-speed connectivity solutions. Backed by CG Power & Industrial Solutions Ltd. part of the 120-year-old Murugappa Group. Axiro represents India’s leap into the global semiconductor arena. With millions of chips already powering global networks, a world-class team across India, the US, and Europe, and cutting-edge expertise spanning RF, mmWave, GaN, and next-generation communication technologies, Axiro is engineering the future of how the world connects, computes, and communicates.For more details – www.axiro.com

Job Description

We seek a highly skilled and experienced Custom IC Layout Lead to manage multiple analog/mixed-signal IC layout projects and lead a team of junior layout engineers. In this role, you will drive full-chip layout execution across a variety of applications and process technologies, while providing technical direction, mentorship, and project oversight. You will collaborate closely with circuit designers, verification teams, program management, and packaging engineers to ensure first-pass silicon success in complex technologies.

Responsibilities

• Execute full custom layout of analog/mixed-signal blocks (e.g., ADCs, DACs, PLLs, LDOs, etc.)
• Lead, mentor, and review the work of a team of junior layout engineers, providing technical guidance and quality oversight
• Plan, prioritize, and manage layout execution across multiple concurrent projects, coordinating schedules and resources to meet tapeout deadlines
• Drive layout strategy and technology qualification across multiple process nodes and technologies (e.g., CMOS, SiGe, BiCMOS, SOI, BCD)
• Collaborate with design engineers to optimize layout for performance, area, and reliability
• Perform layout verification, including DRC, LVS, and parasitic extraction
• Apply layout techniques to mitigate issues such as crosstalk, IR drop, and latch-up
• Provide support for post-layout simulations and tapeout activities
• Maintain design documentation and participate in peer layout reviews
• Interface with packaging and assembly teams to ensure compliance with manufacturing rules
• Work with the design and the foundry team for wafer step plan and wafer matrix

Requirements

• Experience: 12-15 years of hands-on experience in RFIC/MMIC/analog/mixed-signal/custom layout design across multiple process technologies (e.g., CMOS, SiGe, BiCMOS, SOI, BCD), including experience managing multiple concurrent projects and mentoring junior layout engineers.
• Leadership & Project Management:
  • Proven track record managing multiple layout projects simultaneously, from planning through tapeout
  • Experience leading, mentoring, and reviewing the work of junior layout engineers, including technical training and career development
  • Strong cross-functional coordination with design, verification, program management, and foundry teams to align priorities and schedules
• Technical Expertise:
  • Proficient in analog and mixed-signal layout design, including ADCs, DACs, PLLs, DC-DC converters, LDOs, Bandgap references, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers
  • Exposure to RF layout techniques and components such as LNA, MIXER, VCO, RX, and TX is a strong plus
• Process Knowledge: Proven experience working across multiple process technologies, including SiGe, BiCMOS, SOI, and BCD, with the ability to ramp new nodes quickly and guide the team through technology-specific layout considerations
• Layout Fundamentals: Deep understanding of matching, electromigration, latch-up, coupling, cross-talk, IR drop, and parasitic considerations
• Experienced with Cadence and Calibre tools in a Linux environment
• Scripting skills in SKILL and Perl are desirable
• Design Awareness: Ability to interpret and implement design constraints into high-quality, manufacturable layouts
• Cross-Disciplinary Knowledge: Familiarity with package and assembly rules is a plus
• Soft Skills:
  • Strong problem-solving and debugging skills
  • Effective communication and teamwork
  • Flexible, adaptable, and collaborative working style
  • Proven leadership skills, including mentoring, delegating, and providing performance feedback to junior engineers
  • Strong organizational skills to manage multiple projects and competing priorities