senior IC layout engineer

ASTRAWAVE TECHNOLOGY; Santo Niño 1st; On-site; PHP 700,000 - 1,200,000; Full time

Job summary

ASTRAWAVE TECHNOLOGY in the Philippines seeks experienced analog/mixed-signal layout and CAD designers to join our team in developing high speed/RF solutions that will complement our existing products. You will work with circuit design engineers to optimize layouts to meet specifications, participate in post-layout adjustments, and provide layout guidance to juniors to ensure high-quality layouts.

You will also leverage Cadence tools for pcell development and automation (Perl/Python/Tcl) and

Qualifications

• Diploma or bachelor’s in electrical/computer/electronics engineering or equivalent.
• 6+ years hands-on experience in layout engineering.
• Experience on technology node below 16nm and high-speed/RF layout.
• Experience with Cadence tools and pcell development; scripting in Perl/Python/Tcl for automation.

Responsibilities

• Realize layout design from schematic presentation.
• Layout implementation includes floor planning and device placement; power and signal routing; integrity optimization.
• Perform DRC/LVS/ERC/ANT/ESD/PERC/LVL checks and other Physical Verification tasks.
• Pass DRC rules and ensure LVS compliance; prepare materials and review layouts.
• Contribute to layout methodology and enhancement; participate in post-layout adjustments and block/IP activities.

Skills

Analog layout

RF layout

Schematic-to-layout

Team collaboration

Education

Diploma or Bachelor's in electrical/computer/electronics engineering

Tools

Cadence

Pcell scripting (Perl/Python/Tcl)

Job description

Job Description

The Role

ASTRAWAVE develops chips for Data Processing, IP Licensing, Network, Bus, Chiplet Interconnect as well as Chip Customization for different customers. We are currently seeking experienced analog mixed signal layout and CAD designers to join our team in the development of high speed/RF solutions which will be used to complement our current products.

The Person

Work closely with circuit design engineers to optimize layout to meet specification.

Team player and strong commitment to schedules.

Able to work in a multi-cultural environment.

Key Responsibilities

Realize layout design from schematic presentation.

Layout design implementation includes the following functions:

• Floor planning and device placement
• Power and Signal routings and Integrity optimization
• DRC/LVS/ERC/ANT/ESD/PERC/LVL and necessary Physical Verification
• Passing DRC rules and ensuring LVS
• Preparing material and reviewing of layout
• Checklist/Methodology to ensure quality of layout
• Layout methodology and enhancement

Participate in post layout adjustments and block/IP activities.

Good understanding of AMS layout fundamentals/EMIR/RC delay/DecouplingCaps/Latch-up.

Preferred Experience

Experience working on technology node below 16nm.

Experience working on high-speed or RF layout.

Experience in TX/RX/PLL/ADC/DAC/etc. is a plus.

Experience working with Cadence skills or equivalent tools for pcell development(perl/python/tcl) and automation to increase layout productivity.

Understanding of process technology and circuit design.

Understanding of analog layout physical verification CAD setup.

At least 6 years of hands-on working experience in layout engineering.

Experience working with leading industry CAD tools, methodology and finfet technology.

Experience with analog/digital on top (chip-top) integration is a plus point.

Providing layout guidance to juniors ensuring quality layouts.

Academic Credentials

Diploma or bachelor’s in electrical/computer/electronics engineering or equivalent.