Senior Designer, Systems (Computer)

Starfive International; Santo Niño 1st; On-site; PHP 800,000 - 1,200,000; Full time

Job summary

StarFive International is seeking a talented RTL Design Engineer to join its RISC‑V CPU/SoC team. You will design, implement and optimize SystemVerilog modules and collaborate with architects, verification and backend teams to balance timing, power and area.

You should have a strong foundation in digital design and processor microarchitecture, plus experience with SystemVerilog and programming languages. The role offers a challenging, fast‑paced environment in a growing semiconductor company.

Qualifications

• BS/MS/PhD with course work in Electrical Engineering, Computer Architecture, or related fields.
• Strong knowledge of digital design fundamentals including FSMs and timing.
• Proficient in SystemVerilog for RTL design.
• Experience with C/C++ and scripting (Perl/Python) is a plus.
• Comfortable in Linux server environments.

Responsibilities

• Design, implement and improve RTL modules using SystemVerilog.
• Translate design requirements into microarchitecture specifications and clean, synthesizable RTL.
• Maintain clear design documentation, including interface definitions and timing diagrams.
• Own functional modules through development cycle; collaborate with architects, verification, and backend teams.

Skills

SystemVerilog

C/C++

Perl/Python

Digital design fundamentals

Processor microarchitecture

Education

Bachelor's/Master's/PhD in Electrical Engineering or Computer Architecture/Systems Engineering/Software Development

Tools

Linux

Job description

StarFive is a leading provider of RISC-V processors, platforms and solutions. StarFive products are widely used in smart home appliances, smart monitoring, industrial robots, traffic management, intelligent logistics, wearable devices, solid state storage, network communications and edge computing, etc.

We are intensively designing next generation high performance RISC‑V CPU and RISC‑V-based SoC chips. Talents who are passionate in research and development for future chips are welcomed to join us. Being part of this vibrant team, you can produce world class successful commercial chips supported by efficient software stacks.

Responsibilities：

• Design, implement and improve RTL modules using SystemVerilog.
• Translate design requirements into microarchitecture specifications and clean, synthesizable, timing-friendly RTL, including: the design of multi‑stage pipelines, finite state machines, and interfaces to vendor‑specific high‑performance SRAM libraries.
• Maintain clear design documentation, including interface definitions, design assumptions, pipeline timing diagrams, register transitions and other details.
• Own functional modules throughout the development cycle. Responsibilities of an RTL module owner includes: Work closely with architects to refine design specifications and evaluate performance, power, and area trade‑offs. Work closely with verification engineers to define test plans, debug failures, improve functional coverage and fix functional bugs. Work closely with backend engineers to improve the physical design feasibility, including lint, synthesis, and balance timing/area/power goals.

Qualification：

• BS/MS/PHD with course work in Electrical Engineering/Computer Architecture/Systems Engineering/Software Development
• Having basic knowledge of modern processor microarchitecture
• Strong knowledge of digital design fundamentals, such as combinational and sequential logic, truth tables, finite state machines, setup/hold time of flip‑flops
• Proficient in SystemVerilog for RTL design.
• Experience with in C/C++ and scripting languages (Perl/Python) is a plus
• Comfortable working in Linux server environment
• Strong interpersonal skills, written and oral; good team player
• Curiosity to learn and execute at a fast pace; communicate effectively with mentors and other team members