Emulation Test Engineer - HDL/Verilog & VHDL

Siemens AG; Hinoba-an; On-site; PHP 464,000 - 729,000; Full time

Job summary

Siemens AG in Noida (Siemens EDA) seeks an engineer to develop and implement emulation test plans to validate sophisticated semiconductor products. You will leverage Verilog and VHDL to design, implement, and debug emulation models, collaborating with design, verification, and software teams.

This full-time role emphasizes reliability and performance before market release, with opportunities to work across locations and contribute to cutting-edge digital systems.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field.
• 1+ years of experience.
• Experience with HDL languages (Verilog, VHDL) and digital design.
• Strong background in emulation and validation of complex digital systems.
• Excellent problem-solving skills and attention to detail.

Responsibilities

• Develop and implement emulation test plans for product validation.
• Use HDL languages (Verilog, VHDL) to design, implement, and debug emulation models.
• Collaborate with design, verification, and software teams to identify and resolve issues.

Skills

Verilog

VHDL

Digital design

Education

Bachelor's or Master's degree in Electrical/Electronics Engineering

Job description

Siemens AG in Noida (Siemens EDA) seeks an engineer to develop and implement emulation test plans to validate sophisticated semiconductor products. You will leverage Verilog and VHDL to design, implement, and debug emulation models, collaborating with design, verification, and software teams.

This full-time role emphasizes reliability and performance before market release, with opportunities to work across locations and contribute to cutting-edge digital systems.