SoC Architect (Hybrid) - Visas Supported

European Tech Recruit; Randstad; On-site; EUR 110,000 - 170,000; Full time

Job summary

European Tech Recruit is seeking a seasoned SOC Architect to join a pioneering semiconductor scale-up focused on Digital-RF based wireless CMOS solutions and IPs.

You will define the high-level SoC architecture and collaborate with hardware, firmware, and GNSS teams to ensure efficient software execution and scalable, secure designs for future generations. A leadership impact on timelines and budgets is expected.

Qualifications

• 10+ years experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.
• Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (SRAM, ROM, Flash, NVMe…).
• 8 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace, Test (DFT, JTAG, Scan, BIST).
• Solid understanding of chip packaging.
• Proficient in hardware-software interface design, including device drivers, firmware, and low-level software optimizations.
• Strong problem-solving skills for SoC integration, performance, and power efficiency.
• Experienced with silicon bring-up, validation, and post-silicon debug methodologies.
• Deep understanding of peripherals, Pin Function Assignment, multimode interfaces (MIPI, LVDS, SPI, I2C, UART).
• RF/Analog interface design including PLL, ADC, DAC, LNA, PA, DCDC, LDO; layout constraints for noise control.
• Knowledge of low-power design techniques: clock gating, power gating, UPF/CPF.
• Library selection and leakage-power aware design.
• Hands-on IP selection to meet design needs.
• Signal integrity, IO technologies, and power-efficient design.
• Clock and reset networks with low jitter and reset synchronization.
• Power sequencing: wake, sleep, and deep sleep modes.

Responsibilities

• System Design & Integration
• Guide chip physical design with hardware teams
• Coordinate with firmware & GNSS to ensure architecture supports software
• Define and implement security features for SoC
• Keep SoC architecture scalable for future generations
• Manage timelines and deliverables to meet budgets

Skills

RTL Design

RTL Verification

CPU Architecture

ARM MCUs Subsystems

Memory Controllers

Memory Architectures

Digital ASIC Flows

DFT/ JTAG/ Scan/ BIST

HW-SW Interface

Power Optimisation

Silicon Bring-up

Peripherals Interfaces

RF/Analog Interface

Clock/Reset Architecture

Low-Power Techniques

IP Selection

Signal Integrity

Tools

DFT Tools

FPGA/ASIC Flows

Job description

A fantastic opportunity for a skilled SOC Architect to join a pioneering Semiconductor Scale-up, who specialise in innovative Digital-RF based wireless scalable CMOS solutions and related IPs.

You will be responsible for defining the high-level architecture of the SoC, determining which components will be included on the chip. Aside from contributing to a ground-breaking technology, you will be helping shape a team that’s redefining what it means to work in deep tech.

Key Responsibilities

• System Design & Integration


• You will collaborate with the hardware design teams to guide the implementation of the chip's physical design.


• You will coordinate with our firmware & GNSS team to ensure the SoC Architecture supports efficient execution of software, including drivers, operating systems and applications.


• You will define and implement security features to protect the SoC from vulnerabilities.


• You will keep up with the advances in the semiconductor industry and make sure the SoC architecture remains scalable and adaptable for future generations of products.


• Managing product timelines and deliverables, making sure that the SoC Development follows the planned schedule and stays within budget.

Requirements

• 10+ years experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.


• Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe…).


• 8 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).


• Solid understanding of chip packaging.


• Proficient in hardware-software interface design, including device drivers, firmware, and low-level software optimizations.


• Strong problem-solving skills to troubleshoot and resolve architectural issues related to SoC integration, performance, and power efficiency.


• Experienced with silicon bring-up, validation, and post-silicon debug methodologies.


• Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).


• Experience in analog-digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO… integration, and layout constraints for minimizing noise and signal interference.


• Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).


• Deep understanding of library selection and design, with a focus on leakage power-aware methodologies to optimize performance and power trade-offs.


• Hands-on experience with IP selection to meet the specific needs of the design.


• Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.


• In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.


• Solid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency.


• Solid Knowledge in signal processing, communication system.


• Exposure to all aspects of RFIC system design.

By applying to this role you understand that we may collect your personal data, store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/wp-content/uploads/2025/01/European-Tech-Recruit-Privacy-Notice-2025.pdf)