Senior UVM Specialist

The Member Company.

Eindhoven

Hybrid

EUR 55,000 - 75,000

Full time

14 days+
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Job summary

TMC Electronics in Eindhoven is looking for an experienced UVM verification specialist to develop and verify UVM testbenches for FPGA applications. You will specify architectures and verification plans, understand FPGA designs in VHDL, and contribute to a range of semiconductor projects.

Join a collaborative team and lead the extension of UVM know‑how, working across different projects and client engagements.

Qualifications

  • Develop and verify UVM testbenches for FPGA applications.
  • Specify architectures, verification plans and strategies.
  • Understand and verify FPGA designs in VHDL.
  • Lead and establish UVM know-how in the team.

Responsibilities

  • Develop and verify UVM testbenches for FPGA applications.
  • Specify architectures, verification plans and strategies.
  • Understand and verify FPGA designs in VHDL.
  • Lead and establish UVM know-how in the team.

Skills

UVM expertise
HDL verification
FPGA concepts

Tools

Verilog
VHDL

Job description

About this vacancy

At TMC Electronics we are a knowledge partner for various electronics and digital design (verification) topics in the Eindhoven region. We support our customers with design in VHDL or Verilog, test and deliver solid HDL. We have a network with more than 25 customers in the field of electronics and a great team of FPGA experts. A relatively growing need in the region is the knowledge on UVM as a verification method. We already have a few experts in our team, but we need to extend this knowledge in order to stay ahead > knowledgeable consultants to advise and implement UVM in our clients’ design cycles.

  • Develop and Verify UVM testbenches for FPGA applications
  • Specify architectures, verification plans and strategies
  • Understand and verify FPGA designs in VHDL
  • Work on a wide range of different applications in the semiconductor industry
  • Work in different Teams and challenging projects
  • Lead and establish UVM know-how in the team
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