Senior Silicon PD Engineer – Remote in Europe, Equity

Axelera AI; Amsterdam; Remote; EUR 120,000 - 180,000; Full time

Benefits offered by this job

Pension plan

Employee insurances

Company shares

Open collaborative culture

Job summary

Axelera AI in the Netherlands is seeking a Senior/Staff Silicon Physical Design Engineer to shape next-generation multi-core in-memory compute SoCs. You will own RTL-to-GDS flows, including synthesis, floorplanning, place-and-route, timing, and physical verification, collaborating with architecture and RTL teams.

You will work with leading EDA tools (Primetime, Innovus, Calibre, Genus, ICC/ICC2, StarRC) and develop automation in Python/Tcl.

Qualifications

• 10+ years of Physical Design experience from RTL to GDS.
• Strong communication and teamwork skills.
• Expertise in all aspects of physical design.
• Hands-on experience with leading EDA tools: Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Calibre.
• Proficiency in clocking techniques and CTS.
• IP integration across various domains.
• Strong scripting skills in Python and Tcl.

Responsibilities

• Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification.
• Constraint generation, timing analysis and optimization.
• Execute clock tree synthesis (CTS) and custom clock-building techniques.
• Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs.
• Utilize EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre.
• Develop automation scripts in Python, Tcl, Bash and contribute to flow development.
• Debug and solve technical challenges related to physical design.

Skills

Physical design

EDA tools

Python scripting

Tcl scripting

Clock tree synthesis

Teamwork

English fluency

Tools

Primetime

StarRC

Genus

Innovus

Design Compiler

ICC/ICC2

FC

Calibre

Redhawk

Job description

Axelera AI in the Netherlands is seeking a Senior/Staff Silicon Physical Design Engineer to shape next-generation multi-core in-memory compute SoCs. You will own RTL-to-GDS flows, including synthesis, floorplanning, place-and-route, timing, and physical verification, collaborating with architecture and RTL teams.

You will work with leading EDA tools (Primetime, Innovus, Calibre, Genus, ICC/ICC2, StarRC) and develop automation in Python/Tcl.