Senior Logical Design Engineer - SoC RTL (Remote)

Axelera AI

Amsterdam

Remote

EUR 90,000 - 150,000

Full time

14 days+
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Benefits offered by this job

Pension plan
Employee insurances
Company shares

Job summary

Axelera AI is seeking a Senior or Staff Logical Design Engineer to join our team at the forefront of AI silicon. You will architect and implement micro-architectures for in-house AI products, focusing on RTL coding, synthesis, and integration of IPs into top-level SoCs.

In this role you will collaborate with architecture, verification, physical design and software teams across 15 countries to deliver high-performance, power-efficient designs.

Qualifications

  • 5+ years in silicon logical design.
  • RTL coding and synthesis expertise.
  • SoC and 3rd‑party IP integration (PCIe, LPDDR).
  • Fluency in Verilog.
  • Mastery of EDA tools for design and verification.
  • Python, shell or Tcl scripting for automation.
  • English communication across a multi-country team.

Responsibilities

  • Collaborate with cross-functional teams to clarify design specifications.
  • Architect and implement advanced micro-architectures for silicon components.
  • Use industry-standard tools to design and optimize digital logic.
  • Conduct RTL coding at block and system levels.
  • Integrate IPs/Sub IPs into the top-level SoC.
  • Perform lint, CDC, and equivalence checks to improve RTL quality.
  • Automate tasks with scripting for efficiency gains.
  • Work with verification engineers to ensure design correctness.
  • Participate in design reviews and contribute technical insights.
  • Coordinate with physical design on DFM/DFT considerations.

Skills

RTL coding
SoC integration
Verilog
Python scripting
Synthesis

Education

Electronics/Electrical Eng or CS degree

Tools

EDA tools

Job description

Axelera AI is seeking a Senior or Staff Logical Design Engineer to join our team at the forefront of AI silicon. You will architect and implement micro-architectures for in-house AI products, focusing on RTL coding, synthesis, and integration of IPs into top-level SoCs.

In this role you will collaborate with architecture, verification, physical design and software teams across 15 countries to deliver high-performance, power-efficient designs.

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