Senior Physical Design Engineer - ASIC Flows + Equity

IC Resources; Rijswijk; On-site; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Stocks

Bonus

Visa sponsorship

Benefits

Job summary

IC Resources in the Netherlands is seeking a Senior Physical Design Engineer to help establish and expand an in-house ASIC implementation team, supporting precision timing and mixed-signal semiconductor products.

You will join a global engineering organisation responsible for implementing and delivering complex digital and mixed-signal ASICs, building physical design methodologies and flows from scratch, working with RTL, analog, verification, and product engineering across RTL-to-GDSII.

Qualifications

• Degree/Master's/PhD in Electronics, Microelectronics, Physics or related field
• Proven experience delivering complex ASICs through tape-out
• Strong expertise across RTL-to-GDSII implementation flow
• FLOORPLANNING and PnR, CTS, and physical verification
• Advanced STA, timing closure, timing constraints and ECO implementation
• Experience with low-power UPF methodologies
• Signal integrity and power integrity awareness
• Cadence-based physical design flows development from scratch
• Scripting in Tcl, Python, or Perl to automate flows

Responsibilities

• Establish and expand an in-house ASIC implementation team
• Develop robust physical design methodologies and flows
• Collaborate with RTL, analog, verification and product teams to ensure silicon delivery
• Drive timing closure and sign-off across the RTL-to-GDSII flow

Skills

Timing closure

Back-end design

Silicon tape-out

Collaboration

RTL-to-GDSII flow

Scripting (Tcl/Python)

Education

Master's degree in Electronics

PhD in related field

Tools

Cadence tools

Job description

IC Resources in the Netherlands is seeking a Senior Physical Design Engineer to help establish and expand an in-house ASIC implementation team, supporting precision timing and mixed-signal semiconductor products.

You will join a global engineering organisation responsible for implementing and delivering complex digital and mixed-signal ASICs, building physical design methodologies and flows from scratch, working with RTL, analog, verification, and product engineering across RTL-to-GDSII.