Senior Physical Design Engineer

IC Resources; Rijswijk; On-site; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Stocks

Bonus

Visa sponsorship

Benefits

Job summary

IC Resources in the Netherlands is seeking a Senior Physical Design Engineer to help establish and expand an in-house ASIC implementation team, supporting precision timing and mixed-signal semiconductor products.

You will join a global engineering organisation responsible for implementing and delivering complex digital and mixed-signal ASICs, building physical design methodologies and flows from scratch, working with RTL, analog, verification, and product engineering across RTL-to-GDSII.

Qualifications

• Degree/Master's/PhD in Electronics, Microelectronics, Physics or related field
• Proven experience delivering complex ASICs through tape-out
• Strong expertise across RTL-to-GDSII implementation flow
• FLOORPLANNING and PnR, CTS, and physical verification
• Advanced STA, timing closure, timing constraints and ECO implementation
• Experience with low-power UPF methodologies
• Signal integrity and power integrity awareness
• Cadence-based physical design flows development from scratch
• Scripting in Tcl, Python, or Perl to automate flows

Responsibilities

• Establish and expand an in-house ASIC implementation team
• Develop robust physical design methodologies and flows
• Collaborate with RTL, analog, verification and product teams to ensure silicon delivery
• Drive timing closure and sign-off across the RTL-to-GDSII flow

Skills

Timing closure

Back-end design

Silicon tape-out

Collaboration

RTL-to-GDSII flow

Scripting (Tcl/Python)

Education

Master's degree in Electronics

PhD in related field

Tools

Cadence tools

Job description

A major US semiconductor manufacturer is looking for a Senior Physical Design Engineer to help establish and expand its in-house ASIC implementation team, supporting the development of cutting-edge precision timing and mixed-signal semiconductor products.

You will join a highly successful global engineering organisation responsible for the implementation and delivery of complex digital and mixed-signal ASICs. This is a unique opportunity to play a key role in building physical design methodologies and flows from the ground up, working closely with RTL, analog, verification, and product engineering teams across the full RTL-to-GDSII flow.

The desired applicant for the role of Senior Physical Design Engineer will have strong backend implementation expertise, excellent timing closure knowledge, and experience developing robust physical design methodologies using Cadence tools. Experience across low-power and mixed-signal designs would be highly advantageous.

Requirements:

• Degree / Masters / Doctorate in Electronics, Microelectronics, Physics, Computer Engineering, or a related field
• Strong industry experience delivering complex ASICs through successful tape-out
• Proven expertise across the full RTL-to-GDSII implementation flow
• Floorplanning, power planning, power grid design, place and route (PnR), clock tree synthesis (CTS), and physical verification
• Advanced Static Timing Analysis (STA), timing closure, timing constraints, and ECO implementation
• Experience with low-power implementation methodologies and UPF
• Strong understanding of signal integrity, power integrity, EM/IR analysis, and physical sign-off
• Experience developing, maintaining, or building Cadence-based physical design flows and methodologies from scratch
• Scripting and automation skills using Tcl, Python, Perl, or Shell scripting
• Ability to work closely with front-end, verification, and analog teams to achieve successful silicon delivery

Excellent salaries, benefits, stocks, bonus, and visa sponsorship are all available for the correctly qualified candidate.

Tel - 01189073075

LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/