Senior MEMS Timing Verification Engineer – Equity

SiTime Corp.; Rijswijk; Remote; EUR 85,000 - 110,000; Full time

Benefits offered by this job

Equity

Performance bonus

Global collaboration

Job summary

SiTime Corp. in the Netherlands is hiring a Senior Verification Engineer to advance MEMS timing IC verification using SystemVerilog, UVM, and SVA. You will develop verification plans, RNM models, and ensure robust tape-out readiness while coordinating with global teams.

The role requires strong English communication, hands-on Cadence Virtuoso experience, and proficiency with Verilog-based designs in a fast-paced environment.

Qualifications

• MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of work experience doing verification in the semiconductor industry.
• Good verbal and written communication skills in English
• Proficient in SystemVerilog and SystemVerilog OOP
• Fluency in scripting languages such as Perl / Python
• Proficient in verification using UVM
• Strong experience writing SystemVerilog Assertions (SVA)
• Understanding of Analog schematic and experience with Cadence Virtuoso
• Basic understanding of digital design using Verilog
• Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers
• Ability to work independently and drive solutions to challenging problems

Responsibilities

• Developing SV-RNM models for both analog and mixed-signal circuits
• Developing verification plan from chip or block specifications
• Defining and writing System Verilog Assertions (SVA)
• Defining and writing functional coverages and covergroups
• Running simulations and debugging simulation results
• Reviewing verification results for Tape-out sign-off
• Communicating with stakeholders (design/test/verification) to facilitate teamwork and exchange of information

Skills

SystemVerilog

UVM

SVA

SystemVerilog OOP

Perl / Python scripting

Cadence Virtuoso

Verilog

English communication

Education

MS/BS in Electrical/Computer Engineering

Tools

Cadence Virtuoso

SystemVerilog simulators

Job description

SiTime Corp. in the Netherlands is hiring a Senior Verification Engineer to advance MEMS timing IC verification using SystemVerilog, UVM, and SVA. You will develop verification plans, RNM models, and ensure robust tape-out readiness while coordinating with global teams.

The role requires strong English communication, hands-on Cadence Virtuoso experience, and proficiency with Verilog-based designs in a fast-paced environment.