Senior Analog/Mixed-Signal Design Engineer — MEMS Timing

SiTime Corp.; Rijswijk; Remote; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Equity grants

Quarterly bonus

Job summary

SiTime Corp. in the Netherlands seeks an Analog Mixed-Signal Circuit Design Engineer to build precision timing circuits using MEMS technology for high-performance networking, ultra-low power mobile platforms, and wearables.

The role requires an MS or PhD in Electrical Engineering with proven silicon experience. You will design, simulate, verify, and collaborate across functions to deliver blocks that meet stringent specs, while supporting chip bring-up and characterization.

Qualifications

• MS or PhD in Electrical Engineering.
• Excellent academic record with published research prototyped in silicon.
• Detailed knowledge of CMOS circuits and noise analysis.
• Graduate coursework and design expertise in analog blocks such as PLLs, sensors, ADCs, filters, amplifiers, regulators.

Responsibilities

• Design analog and mixed-signal circuits meeting architectural specs.
• Contribute to architectural definition and chip integration.
• Perform schematic and post-layout verification simulations with DFT/DFM provisioning.
• Coordinate with Layout Engineers to validate layout quality.
• Document blocks and lead design reviews.
• Support chip bring-up, evaluation and characterization of owned blocks.
• Collaborate with Product, Characterization, Test, and Application Engineers.

Skills

CMOS circuits

Noise analysis

Schematic/design

MATLAB

VerilogA

Cadence tools

Education

MS/PhD in Electrical Engineering

Tools

Cadence

VerilogA

MATLAB

Job description

SiTime Corp. in the Netherlands seeks an Analog Mixed-Signal Circuit Design Engineer to build precision timing circuits using MEMS technology for high-performance networking, ultra-low power mobile platforms, and wearables.

The role requires an MS or PhD in Electrical Engineering with proven silicon experience. You will design, simulate, verify, and collaborate across functions to deliver blocks that meet stringent specs, while supporting chip bring-up and characterization.