Test Engineer (Pioneer role, Chip Design House)

Career International FOS Pte Ltd; Bayan Lepas; On-site; MYR 60,000 - 96,000; Full time

Job summary

Career International FOS Pte Ltd in Penang, Malaysia is seeking an engineer to develop ATE test plans in collaboration with DFT, ensuring coverage of chip design requirements.

You will develop CP/FT test programs and hardware, design load boards and probe cards, and contribute to NPI validation and mass production optimization, while collaborating with R&D and FT teams to meet schedules and quality targets.

Qualifications

• Experience with ATE test flows and CP/FT hardware design.
• Familiar with large-chip testing and DFT concepts.
• Proficient in VB/C/C++ programming and debugging tools.

Responsibilities

• Develop ATE test plans in collaboration with DFT, ensuring coverage.
• Develop CP/FT test programs and hardware; design test tooling.
• Lead engineering validation and mass production optimization efforts.
• Collaborate with R&D and FT teams to meet schedules and quality targets.

Skills

ATE test flows

CP/FT test hardware design

VB/C/C++ programming

JTAG/SCAN/MBIST

Large-chip testing

Tools

Load Board

Probe Card

NPI test infrastructure

Job description

Develop ATE test plans: Collaborate with DFT to define test plans based on chip design requirements and ensure test coverage.

Develop test programs and hardware: Responsible for CP/FT test program development, debugging, and vector preparation; design test hardware such as Load Board and Probe Card, and produce related documentation.

Engineering validation and mass production optimization: Develop NPI engineering validation programs such as CHAR/DVS/HTOL; continuously optimize test solutions during mass production to improve coverage, reduce test cost, resolve stability issues, and support yield analysis and failure analysis.

Capacity build-up and team collaboration: Responsible for mass production tooling validation and management to meet capacity targets; collaborate with R&D and FT test teams on binning tests to ensure project schedule and quality.

Requirements

Experience preferred: Experience in large-chip testing is preferred.

Core competency: Familiar with ATE test flows and capable of CP/FT test hardware design.

Platform and programming: Familiar with mainstream platforms such as 93K and UltraFlex; able to independently develop logic IC production test programs; strong software programming and debugging skills (e.g., VB/C/C++).

DFT and SOC knowledge: Familiar with DFT fundamentals (e.g., JTAG/SCAN/MBIST); experience in high-power SOC chip testing.