ATE Engineer (Test Engineer)

Career International 科锐国际; Penang; On-site; MYR 60,000 - 100,000; Full time

Job summary

Career International 科锐国际 in Penang seeks an experienced semiconductor test engineer to develop ATE test plans and hardware for large-chip devices. You will collaborate with DFT teams to ensure full test coverage and robust CP/FT implementations.

The role focuses on engineering validation for NPI, optimizing test solutions during mass production, and working with R&D and FT teams on binning tests to meet schedules and quality targets.

Qualifications

• Experience in large-chip testing is preferred.
• Familiar with ATE test flows and capable of CP/FT test hardware design.
• Familiar with mainstream platforms such as 93K and UltraFlex; able to independently develop logic IC production test programs; strong software programming and debugging skills (VB/C/C++).
• Familiar with DFT fundamentals (e.g., JTAG/SCAN/MBIST); experience in high-power SOC chip testing.

Responsibilities

• Develop ATE test plans collaborating with DFT to define plans and ensure coverage.
• Develop test programs and hardware; design test hardware such as Load Board and Probe Card; produce documentation.
• Drive engineering validation and mass-production optimization; develop NPI validation programs (CHAR/DVS/HTOL) and improve test coverage and cost.
• Support capacity build-up; collaborate with R&D and FT teams on binning tests to meet schedule and quality.

Skills

ATE test flows

CP/FT test hardware design

VB/C/C++ programming

DFT fundamentals

JTAG/SCAN/MBIST

SOC testing

Tools

93K platform

UltraFlex platform

Job description

• Develop ATE test plans: Collaborate with DFT to define test plans based on chip design requirements and ensure test coverage.
• Develop test programs and hardware: Responsible for CP/FT test program development, debugging, and vector preparation; design test hardware such as Load Board and Probe Card, and produce related documentation.
• Engineering validation and mass production optimization: Develop NPI engineering validation programs such as CHAR/DVS/HTOL; continuously optimize test solutions during mass production to improve coverage, reduce test cost, resolve stability issues, and support yield analysis and failure analysis.
• Capacity build-up and team collaboration: Responsible for mass production tooling validation and management to meet capacity targets; collaborate with R&D and FT test teams on binning tests to ensure project schedule and quality.

Requirements

• Experience preferred: Experience in large-chip testing is preferred.
• Core competency: Familiar with ATE test flows and capable of CP/FT test hardware design.
• Platform and programming: Familiar with mainstream platforms such as 93K and UltraFlex; able to independently develop logic IC production test programs; strong software programming and debugging skills (e.g., VB/C/C++).
• DFT and SOC knowledge: Familiar with DFT fundamentals (e.g., JTAG/SCAN/MBIST); experience in high-power SOC chip testing.