Senior FPGA Validation & Automation Engineer

Altera Corporation; Kuala Lumpur; On-site; MYR 180,000 - 260,000; Full time

Job summary

Altera Corporation in Malaysia is seeking a senior engineer for the Device Modeling & Enablement team. You will develop and automate tests validating FPGA device and simulation models used by Quartus Prime, drive end-to-end validation, and maintain regression infrastructure for high-quality releases across multiple device families.

The role emphasizes a strong foundation in digital design, FPGA/ASIC flows, automation with C++, Tcl, Python, and a commitment to quality and continuous improvement.

Qualifications

• BS/MS/PhD in Electrical/Computer Engineering or related field.
• 4–5 years of relevant experience in FPGA/ASIC design or testing.
• Strong foundations in digital design and timing concepts.
• Experience with RTL languages and FPGA toolchains (Verilog/SystemVerilog, VHDL, SDC).
• Proficiency in scripting (Tcl/Python) and C++ for modeling/debugging.
• Familiarity with Linux development environments and build workflows.

Responsibilities

• Develop test plans for device and simulation model validation across Quartus Prime components.
• Execute regression tests across FPGA families and configurations; ensure coverage.
• Build and maintain end-to-end Quartus projects for synthesis, fitting, and simulation signoff.
• Create and maintain automation tools and C++ device model libraries.
• Integrate tests into CI pipelines with pass/fail gates and artifact tracking.
• Analyze failures, triage root causes, and improve repeatability and quality.

Skills

Digital design

FPGA/ASIC flows

RTL Verilog/SystemVerilog

VHDL

C++ for modeling

Python

Tcl scripting

Linux development

Debug & problem-solving

Documentation & communication

Education

BS/MS/PhD in ECE/CE/CS

Tools

Quartus Prime

Git

Jenkins/GitLab CI

TimeQuest

Job description

Altera Corporation in Malaysia is seeking a senior engineer for the Device Modeling & Enablement team. You will develop and automate tests validating FPGA device and simulation models used by Quartus Prime, drive end-to-end validation, and maintain regression infrastructure for high-quality releases across multiple device families.

The role emphasizes a strong foundation in digital design, FPGA/ASIC flows, automation with C++, Tcl, Python, and a commitment to quality and continuous improvement.