Senior Formal Verification Engineer - Next-Gen SoC/ASIC

AMD; George Town; On-site; MYR 180,000 - 300,000; Full time

Job summary

AMD in Penang, Malaysia is seeking an experienced Design Verification engineer to advance pre-silicon IP verification quality for ASIC/SOC designs. You will port and build Formal Verification environments, develop test plans, and drive coverage analysis and regression cleanup across blocks and IPs.

The role requires strong analytical skills, mentoring capability, and the ability to guide FV tasks through to completion while collaborating with cross-functional teams.

Qualifications

• Strong analytical and problem solving skills with a pronounced attention to detail.
• Excellent communication, mentoring and leadership skills.
• Experience driving teams and tasks from start to finish with high quality.
• Ability to work with cross-functional teams.

Responsibilities

• Apply current functional verification techniques to improve pre-silicon IP verification quality and product Time to Market for ASIC/SOC design.
• Port and create the Formal Verification environment for new designs, block and IP level test plan creation and implementation, coverage analysis, and regression cleanup.
• Work independently on various FV tasks and provide technical guidance to the FV team.

Skills

SV/UVM

Formal Verification

Processor architectures

AMBA bus protocol

PCIe protocol

Education

Bachelor's or Master's in Computer/Electrical Engineering

Tools

SV/UVM

Formal Verification

Testbenches

Job description

AMD in Penang, Malaysia is seeking an experienced Design Verification engineer to advance pre-silicon IP verification quality for ASIC/SOC designs. You will port and build Formal Verification environments, develop test plans, and drive coverage analysis and regression cleanup across blocks and IPs.

The role requires strong analytical skills, mentoring capability, and the ability to guide FV tasks through to completion while collaborating with cross-functional teams.