Senior Digital IC Physical Design Engineer

Bell Ward; Shah Alam; On-site; MYR 90,000 - 150,000; Full time

Job summary

Jora Malaysia in Shah Alam is partnering with a global semiconductor leader to hire Physical Design Engineers passionate about next‑generation chip development. If you have experience in digital physical design and want to work with international teams on cutting‑edge technology, this role could be a strong fit.

Key responsibilities include leading RTL to GDSII flow, P&R, CTS, STA, power integrity, DRC/LVS, and silicon delivery support with cross‑functional engineers.

Qualifications

• Bachelor's Degree in Electrical/Electronics/Computer Engineering or related field.
• 3–10 years in digital LSI or ASIC physical design.
• Strong RTL-to-GDSII implementation experience.
• Proficiency with Synopsys, Cadence, Siemens EDA, or equivalents.
• Solid understanding of physical implementation, timing closure, optimization techniques, and design verification.
• Strong analytical thinking and debugging skills.
• Effective communication and collaboration in multidisciplinary teams.
• Experience with 7nm, 5nm, 3nm or advanced nodes.
• Exposure to high-performance and/or low-power SoC/ASIC projects.
• Experience owning design blocks or leading project deliverables is a plus.

Responsibilities

• Execute digital LSI physical design activities across the full implementation flow, from logic synthesis through physical sign-off.
• Develop, optimize, and refine synthesis strategies to meet design, timing, area, and power objectives.
• Drive place-and-route (P&R) activities, including floorplanning, CTS, routing, and physical design optimization.
• Perform STA and timing closure to ensure performance specifications.
• Conduct power integrity analysis and validation to enhance design robustness.
• Carry out physical verification: DRC, LVS, and sign-off checks.
• Collaborate with cross-functional teams to address implementation challenges for silicon delivery.
• Participate in technical reviews and process improvement initiatives to improve design quality.

Skills

Digital LSI design

RTL-to-GDSII flow

EDA tools proficiency

Physical implementation

Education

Bachelor's Degree in EE/EC/CE

Tools

Synopsys

Cadence

Siemens EDA

Job description

Jora Malaysia in Shah Alam is partnering with a global semiconductor leader to hire Physical Design Engineers passionate about next‑generation chip development. If you have experience in digital physical design and want to work with international teams on cutting‑edge technology, this role could be a strong fit.

Key responsibilities include leading RTL to GDSII flow, P&R, CTS, STA, power integrity, DRC/LVS, and silicon delivery support with cross‑functional engineers.