Senior/Staff Mid-End Engineer (STA/Synthesis)

Bitdeer Technologies Group; Seberang Perai; Sur place; MYR 180 000 - 280 000; Plein temps

Résumé du poste

Bitdeer Technologies Group seeks a seasoned IC design engineer in Penang to drive synthesis, timing closure, and power optimization for ASIC designs. You will collaborate with DFT and physical design teams to optimize floorplans, P&R, and timing bottlenecks while ensuring formal verification of netlists.

The ideal candidate has 3–7 years in IC design, solid Verilog/SystemVerilog skills, and hands-on experience with leading EDA tools and multi-clock domains.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3–7 years of IC design experience focusing on synthesis, timing closure, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Synopsys Design Compiler, Cadence Genus, PrimeTime, Innovus).
• Strong understanding of timing analysis, multi-clock domain handling, and clock tree synthesis.
• Familiarity with on-chip interconnect architectures (AXI, NoC, mesh, torus).
• Experience in low-power design methodologies (UPF, power gating, dynamic voltage scaling).
• Proficiency in scripting (TCL, Python, Perl, Shell) for automation.

Responsabilités

• Synthesis & Logic Optimization for ASIC designs.
• STA, timing closure, and clock tree optimization for high-frequency data pipelines.
• Power & area optimization using low-power techniques; collaborate with DFT engineers.
• Work with Physical Design teams for floorplanning, P&R, and timing bottlenecks.
• Formal verification & equivalence checking using formal tools.

Connaissances

Verilog/SystemVerilog

RTL-to-GDSII flow

EDA tools

Timing analysis

Multi-clock domains

Clock tree synthesis

Scripting

NoC interconnects

Formation

Bachelor’s or Master’s degree in Electrical/Computer Eng

Outils

Synopsys Design Compiler

Cadence Genus

PrimeTime

Innovus

Description du poste

About Bitdeer:

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.
Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence.
Headquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia.

What you'll do:

• Synthesis & Logic Optimization:
  • Perform logic synthesis and design optimization for ASIC designs.
• Static Timing Analysis (STA) & Timing Closure:
  • Conduct STA, constraint tuning, and clock tree synthesis (CTS) to optimize critical paths.
  • Resolve timing issues related to multi-clock domains and high-frequency data pipelines.
• Power & Area Optimization:
  • Implement low-power design techniques (clock gating, power gating, dynamic voltage scaling) for specific workloads.
  • Work on memory hierarchy optimization to reduce energy consumption.
  • Collaborate with DFT engineers for scan chain insertion, MBIST for large SRAMs, and JTAG integration.
  • Debug synthesis, timing, and power-related design issues before physical implementation.
• Collaboration with Physical Design Team:
  • Work closely with backend teams on floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.
  • Provide design constraints for specific architectures, such as high-speed interconnects, NoCs (Network-on-Chip), and large-scale data movement.
• Formal Verification & Equivalence Checking:
  • Ensure synthesized netlist correctness using formal verification tools (Conformal, FormalPro, JasperGold).

Required qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3–7 years of experience in IC design with a focus on synthesis, timing closure, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Synopsys Design Compiler, Cadence Genus, PrimeTime, Innovus).
• Strong understanding of timing analysis, multi-clock domain handling, and clock tree synthesis.
• Familiarity with on-chip interconnect architectures (AXI, NoC, mesh, torus).
• Experience in low-power design methodologies (UPF, power gating, dynamic voltage scaling).
• Proficiency in scripting (TCL, Python, Perl, Shell) for automation.

What you will experience working with us:

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.

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Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.