Senior Analog Layout Engineer: From Block to Chip Design

Infineon Technologies; Malaysia; On-site; MYR 90,000 - 140,000; Full time

Job summary

Infineon Technologies Malaysia seeks an experienced engineer to perform analog circuit block, subsystem, and top‑level layout and verification using state‑of‑the‑art tools, including Cadence Virtuoso‑VXL.

You will participate in layout design of analog circuits, plan floor‑planning from scratch, and handle routing, verification and violations while contributing to design reviews. 2–5 years of hands‑on analog layout experience in sub‑micron CMOS is expected.

Qualifications

• Bachelor's degree in Electrical/Electronics Engineering or Microelectronics with VLSI exposure.
• 2–5 years of analog layout experience, from scratch.
• Experience with IR-drop/EM analysis.
• Strong understanding of matching, parasitic reduction, ESD, DFM in sub-micron CMOS.
• Strong analytical and communication skills; team player.

Responsibilities

• Execute analog circuit block, subsystem and top-level layout and verification using Cadence Virtuoso-VXL.
• Participate in layout design of analog circuits; plan floor‑planning from scratch; perform routing, layout verification and resolve violations.
• Contribute to layout design reviews.
• Plan block‑level schedules.

Skills

Analog layout

Layout verification

VLSI exposure

Problem solving

Cross-functional collaboration

Education

Bachelor's degree in Electrical/Electronics Engineering or Microelectronics

Tools

Cadence Virtuoso-VXL

Job description

Infineon Technologies Malaysia seeks an experienced engineer to perform analog circuit block, subsystem, and top‑level layout and verification using state‑of‑the‑art tools, including Cadence Virtuoso‑VXL.

You will participate in layout design of analog circuits, plan floor‑planning from scratch, and handle routing, verification and violations while contributing to design reviews. 2–5 years of hands‑on analog layout experience in sub‑micron CMOS is expected.