Prototype FPGA Engineer — Physical AI Intern

Lattice Malaysia; Malaysia; On-site; MYR 20,000 - 30,000; Full time

Job summary

Lattice Malaysia invites final-year or penultimate-year students in Electrical, Electronic, Computer Systems or Computer Engineering to join a 12-week placement in Penang (Dec 2026–Feb 2027). You will work on RTL design, FPGA prototype validation, and hardware-software co-design for Physical AI workloads on Lattice Avant and Nexus platforms.

The role involves embedded firmware work, testbenches, debugging across the FPGA cycle, and collaboration with global teams to produce reference designs and

Qualifications

• RTL design and verification (SystemVerilog/Verilog, FSM and datapath design)
• Embedded C/C++ with DMA, interrupts and memory-mapped I/O
• SoC integration with soft-core processors and RTOS is a plus
• Exposure to ML inference deployment or robotics control loops is a plus

Responsibilities

• Design, integrate and validate RTL for FPGA prototypes and soft-IP integration
• Develop hardware-software co-design flows for Physical AI workloads and robot-control pipelines
• Debug across the FPGA development cycle: testbenches, waveform analysis, board bring-up
• Automate validation, CI, telemetry, and test reporting
• Create reference designs and application notes for customer engagements

Skills

RTL design

Verilog/SystemVerilog

FPGA timing closure

Embedded C/C++

Self-checking testbenches

SoC integration

Documentation skills

Cross-team collaboration

Education

Electrical Engineering

Electronic Engineering

Computer Systems

Computer Engineering

Tools

Radiant

Propel

RISC-V

MCU development

Job description

Lattice Malaysia invites final-year or penultimate-year students in Electrical, Electronic, Computer Systems or Computer Engineering to join a 12-week placement in Penang (Dec 2026–Feb 2027). You will work on RTL design, FPGA prototype validation, and hardware-software co-design for Physical AI workloads on Lattice Avant and Nexus platforms.

The role involves embedded firmware work, testbenches, debugging across the FPGA cycle, and collaboration with global teams to produce reference designs and