FPGA System-Level Test & Debug Engineer

Altera; Bayan Lepas; On-site; MYR 90,000 - 120,000; Full time

Job summary

Altera in Penang, Malaysia is seeking a System Level Test (SLT) Engineer to define validation methods and test plans for platform validation. You will drive test planning, data analysis, automation, and debugging to ensure testability and product quality, partnering with hardware, software, and manufacturing teams.

The role emphasizes IP subsystem validation, test coverage, and documentation of risk assessments.

Qualifications

• Bachelor’s / Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience defining and executing system-level, platform, silicon, or product validation plans and test methods.
• Experience developing automated test, regression, or verification scripts; analyzing data; and debugging failures to root cause.
• Experience working cross-functionally with hardware architecture and design, silicon validation, software, integration, process engineering, and manufacturing teams.
• Experience with bench or automatic test equipment validation and characterization of system performance, timing, power, thermal behavior, or hardware-software interaction.

Responsibilities

• Develop test plans, test methods, execution, data analysis, builds automation and regression scripts, and creates automated verification flows for products including FPGA, transceiver, and multi-chip packages.
• Understands IP subsystem validation requirements, including functional tests coverage needs within specifications, and corrective actions are put in place to catch any silicon failures.
• Performs debug to root cause product issues, from production rejects (RV) and/or customer reported failures (FACR) and execute workaround to patch the test holes to improve product quality.
• Works with various cross-functional teams to evaluate integrated system performance and to test and characterize device functionality at various operating conditions.
• Contributes to the product health indicators (PHI) definition and test hole reduction of defects per million (DPM) for quality monitoring.
• Creates platform validation documentation including risk assessments, test plans, user acceptance tests, and reports.

Skills

System-level validation

Test automation

Data analysis

Cross-functional collaboration

Debugging

Education

Bachelor’s / Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Verilog / VHDL

Quartus Prime

TCL

Python

Job description

Altera in Penang, Malaysia is seeking a System Level Test (SLT) Engineer to define validation methods and test plans for platform validation. You will drive test planning, data analysis, automation, and debugging to ensure testability and product quality, partnering with hardware, software, and manufacturing teams.

The role emphasizes IP subsystem validation, test coverage, and documentation of risk assessments.