System Level Test (SLT) Content Development and Debug Engineer

Altera; Bayan Lepas; On-site; MYR 90,000 - 120,000; Full time

Job summary

Altera in Penang, Malaysia is seeking a System Level Test (SLT) Engineer to define validation methods and test plans for platform validation. You will drive test planning, data analysis, automation, and debugging to ensure testability and product quality, partnering with hardware, software, and manufacturing teams.

The role emphasizes IP subsystem validation, test coverage, and documentation of risk assessments.

Qualifications

• Bachelor’s / Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience defining and executing system-level, platform, silicon, or product validation plans and test methods.
• Experience developing automated test, regression, or verification scripts; analyzing data; and debugging failures to root cause.
• Experience working cross-functionally with hardware architecture and design, silicon validation, software, integration, process engineering, and manufacturing teams.
• Experience with bench or automatic test equipment validation and characterization of system performance, timing, power, thermal behavior, or hardware-software interaction.

Responsibilities

• Develop test plans, test methods, execution, data analysis, builds automation and regression scripts, and creates automated verification flows for products including FPGA, transceiver, and multi-chip packages.
• Understands IP subsystem validation requirements, including functional tests coverage needs within specifications, and corrective actions are put in place to catch any silicon failures.
• Performs debug to root cause product issues, from production rejects (RV) and/or customer reported failures (FACR) and execute workaround to patch the test holes to improve product quality.
• Works with various cross-functional teams to evaluate integrated system performance and to test and characterize device functionality at various operating conditions.
• Contributes to the product health indicators (PHI) definition and test hole reduction of defects per million (DPM) for quality monitoring.
• Creates platform validation documentation including risk assessments, test plans, user acceptance tests, and reports.

Skills

System-level validation

Test automation

Data analysis

Cross-functional collaboration

Debugging

Education

Bachelor’s / Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Verilog / VHDL

Quartus Prime

TCL

Python

Job description

About Altera

Altera is a leading FPGA (Field-Programmable Gate Array) company that delivers programmable hardware, software, and development tools to drive innovation from cloud to edge. With over four decades of experience in programmable logic, our broad portfolio includes FPGAs, CPLDs, IP, SmartNICs, IPUs, and System on Modules—supported by industry-leading tools like the Quartus development suite.

Job Description

Altera is a leading FPGA (Field-Programmable Gate Array) company that delivers programmable hardware, software, and development tools to drive innovation from cloud to edge. With over four decades of experience in programmable logic, our broad portfolio includes FPGAs, CPLDs, IP, SmartNICs, IPUs, and System on Modules—supported by industry-leading tools like the Quartus development suite.

Recently re‑established as an independent business, Altera is focused on accelerating programmable compute in AI, networking, communications, industrial, automotive, aerospace/military, and edge‑computing domains. Our mission is to provide leadership programmable solutions that are easy to design and deploy, and our vision is to pioneer innovation that unlocks extraordinary possibilities.

About The Role

We are seeking a System Level Test (SLT) Engineer to define and execute validation methods and test plans for system‑level test and product platform validation. In this role, you will drive test planning, execution, data analysis, automation, and perform debug for test gap resolution to ensure the testability, manufacturability, and quality of Altera products. You will partner across hardware and software engineering, silicon validation, manufacturing and customer support teams to identify issue root causes, improve product health, and deliver platform readiness.

Key Responsibilities

• Develop test plans, test methods, execution, data analysis, builds automation and regression scripts, and creates automated verification flows for products including FPGA, transceiver, and multi‑chip packages on bench or automatic test equipment.
• Understands IP subsystem validation requirements, including functional tests coverage needs within specifications, and corrective actions are put in place to catch any silicon failures.
• Performs debug to root cause product issues, from production rejects (RV) and/or customer reported failures (FACR) and execute workaround to patch the test holes to improve product quality.
• Works with various cross‑functional teams to evaluate integrated system performance and to test and characterize device functionality at various operating conditions.
• Contributes to the product health indicators (PHI) definition and test hole reduction of defects per million (DPM) for quality monitoring.
• Creates platform validation documentation including risk assessments, test plans, user acceptance tests, and reports.

Qualifications

Minimum Qualifications

• Bachelor’s / Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Experience defining and executing system‑level, platform, silicon, or product validation plans and test methods.
• Experience developing automated test, regression, or verification scripts; analyzing data; and debugging failures to root cause.
• Experience working cross‑functionally with hardware architecture and design, silicon validation, software, integration, process engineering, and manufacturing teams.
• Experience with bench or automatic test equipment validation and characterization of system performance, timing, power, thermal behavior, or hardware‑software interaction.

Preferred Qualifications

• Experience in generating test contents and vectors to validate FPGA or multi‑chip package products covering various IP subsystems such as core, configuration, transceiver, HPS, EMIF, LVDS, MIPI etc.
• Experience developing test automation and maintaining test frameworks, regression infrastructure, or enterprise‑service integrations.
• Experience evaluating or deploying platform production test equipment and defining manufacturing test methodologies.
• Knowledge in Verilog / VHDL, Quartus Prime RTL generation including timing closure, and scripting languages such as TCL, Python etc.
• Strong system‑level problem‑solving, data‑analysis, technical communication, and cross‑functional collaboration skills.
• Candidates who are highly motivated, self‑driven, initiative and resourceful would be suitable for this job scope.

Job Type

Regular

Shift

Shift 1 (Malaysia)

Primary Location

Penang 15, Penang, Malaysia

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.