System-Level Test & Debug Engineer for FPGA Platforms

Altera Corporation; Malaysia; On-site; MYR 90,000 - 150,000; Full time

Job summary

Altera is seeking a System Level Test (SLT) Engineer in Penang, Malaysia to define validation methods and test plans for system-level validation. You will partner with hardware, software, silicon validation, manufacturing and support teams to ensure testability, manufacturability and product readiness.

Responsibilities include developing test plans and automated verification flows for FPGA, transceiver and multi-chip packages, performing debug to root causes, and creating platform validation

Qualifications

• Experience defining and executing system-level, platform, silicon, or product validation plans and test methods.
• Experience developing automated test, regression, or verification scripts and debugging failures to root cause.
• Experience working cross-functionally with hardware, silicon validation, software, and manufacturing teams.

Responsibilities

• Develop test plans and automated flows for FPGA, transceiver, and multi-chip packages.
• Perform debug to root cause issues and patch test gaps to improve quality.
• Collaborate with hardware, software, and manufacturing teams to evaluate system performance and operating conditions.
• Create platform validation documentation and risk assessments.

Skills

System-level validation

Test automation

Cross-functional collaboration

Data analysis

Debugging failures

Education

Bachelor’s / Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field

Tools

Verilog

VHDL

TCL

Python

Job description

Altera is seeking a System Level Test (SLT) Engineer in Penang, Malaysia to define validation methods and test plans for system-level validation. You will partner with hardware, software, silicon validation, manufacturing and support teams to ensure testability, manufacturability and product readiness.

Responsibilities include developing test plans and automated verification flows for FPGA, transceiver and multi-chip packages, performing debug to root causes, and creating platform validation