Cadence Virtuoso Layout Trainee - Analog & Mixed-Signal

Collaw

Penang

Presencial

MYR 13.000 - 20.000

Jornada completa

14 días+

Una candidatura completa en un minuto

Currículum y carta de presentación personalizados, listos para enviar.

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Descripción de la vacante

Infineon in Penang, Malaysia is offering an Industrial Trainee role focused on layout design and verification using Cadence Virtuoso tools. The position provides hands-on experience with Infineon layout flow and methodologies, under the guidance of a senior engineer.

Responsibilities include learning Unix commands, performing layout design for basic logic gates, level shifters, and analog mixed-signal layouts with Physical Verification Checks, and completing the Final Year Project under senior

Formación

  • Bachelor's Degree in Microelectronic or Electrical & Electronic.
  • Minimum CGPA 3.00+.
  • Exposure to Cadence Virtuoso and layout verification processes.

Responsabilidades

  • Introduction to Unix commands.
  • Learn and practice Infineon layout flow and methodologies.
  • Engage in hands-on experience using Cadence Virtuoso tools for layout design.
  • Design layouts for basic logic gates, level shifters, and analog mixed signal layouts, including Physical Verification Checks, under the guidance of a senior engineer.
  • Complete Final Year Project under guidance of a senior engineer.

Conocimientos

Unix commands
Cadence Virtuoso
Layout design
Physical Verification

Educación

Bachelor's Degree in Microelectronic or Electrical & Electronic

Herramientas

Cadence Virtuoso

Descripción del empleo

Infineon in Penang, Malaysia is offering an Industrial Trainee role focused on layout design and verification using Cadence Virtuoso tools. The position provides hands-on experience with Infineon layout flow and methodologies, under the guidance of a senior engineer.

Responsibilities include learning Unix commands, performing layout design for basic logic gates, level shifters, and analog mixed-signal layouts with Physical Verification Checks, and completing the Final Year Project under senior

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