Staff Silicon Design Engineer

AMD; George Town; On-site; MYR 180,000 - 280,000; Full time

Job summary

AMD in Penang, Malaysia invites a Senior Front End Integration Silicon Design Engineer to join our ASIC/SoC team. You will drive front-end implementation, RTL-to-netlist flow, and collaborate with PD to deliver high-quality silicon across advanced processes.

Ideal candidates bring 8–10 years in Verilog RTL, front-end EDA toolchains, and proven ability to work across multi-site teams. A degree in Computer or Electrical Engineering is required.

Qualifications

• Solid foundation in ASIC/SoC design and verification.
• Experience with front-end RTL design and verification.
• Hands-on experience developing or applying AI solutions for engineering workflows.

Responsibilities

• Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
• Develop ASIC design methodology and flow, interfacing with EDA vendors on technology.
• Ensure timing, lower power, and netlist quality checks with RTL and PD teams.

Skills

Verilog RTL design

ASIC/SoC design

Front-end EDA tools

Unix/Linux scripting

Team collaboration

Education

Bachelor's or Master's in Computer/Electrical & Electronics Engineering

Tools

Design Compiler

PrimeTime

Conformal

VSI/VC-static

Formality

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

We are seeking a highly motivated Front End Integration Silicon Design Engineer to drive the next generation of silicon development. This role combines traditional RTL design and verification expertise with AI/ML technologies to improve engineering productivity, quality, and development efficiency across the silicon lifecycle. The ideal candidate has a solid foundation in ASIC/SoC design and verification, along with hands‑on experience developing or applying AI solutions for engineering workflows.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. The ideal candidate has a solid foundation in ASIC/SoC design and verification, along with hands‑on experience developing or applying AI solutions for engineering workflows.

Key Responsibilities

• Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
• Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
• Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.

Preferred Experience

• Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
• Experience with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal, VSI/VC-static, Formality, etc…)
• Experience with unix/linux and scripts (tcl, perl, etc.)
• Experience with physical design is a plus.
• Has Synthesis or physical implement experience.
• Experience with lower power design methodology.
• Overall of 8 to 10 years experience for the above.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in Computer Engineering/Electrical & Electronics Engineering.

LOCATION:

Penang, Malaysia

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.