Standard Cell Layout Engineer

Qualcomm; Tijuana; Presencial; MXN 420.000 - 720.000; Jornada completa

Descripción de la vacante

Qualcomm seeks a layout engineer to design and develop physical layouts for logic standard cells using Cadence Virtuoso, with SKILL and Python for automation. You will collaborate with circuit designers to ensure layouts meet performance and reliability requirements, and perform comprehensive layout verification.

Responsibilities include DRC/LVS/ERC checks, managing layout databases, and clear communication of design status within a globally distributed team including the US, Taiwan, and India.

Formación

• Associate degree or technical certificate in CS, Math, EE or related field.
• Foundational CMOS/IC design knowledge.
• Strong attention to detail and ability to work in a collaborative team.

Responsabilidades

• Design and develop physical layouts for logic standard cells using CAD tools like Cadence Virtuoso.
• Perform DRC, LVS, and ERC checks for layout verification.
• Collaborate with circuit designers to meet quality, performance, and reliability requirements.
• Maintain and manage layout databases and design data.
• Communicate design status and milestones with the engineering team.
• Identify and resolve design and PDK-related issues and document solutions.
• Coordinate with global teams (US, Taiwan, India) on layout tasks.

Conocimientos

Scripting & automation

Team collaboration

Attention to detail

Educación

Associate’s degree or technical certificate

Bachelor’s degree preferred

Herramientas

Cadence Virtuoso

Layout design tools

Descripción del empleo

Overview

As a member of the Qualcomm Standard Cell Design team, the candidate will be responsible for contributing to the development of high-quality intellectual property (IP) for advanced semiconductor technology nodes. This role involves applying strong technical expertise and creativity to deliver efficient and scalable physical layout designs within Qualcomm’s structured and methodical design framework. The position offers significant opportunities for professional and engineering growth through exposure to industry-leading design practices and cutting-edge technologies.

Responsibilities

• Design and develop physical layouts for logic standard cells using industry-standard CAD tools, such as Cadence Virtuoso. This role involves leveraging scripting and algorithmic programming languages, including SKILL and Python, to support layout automation, optimization, and design efficiency.
• Perform comprehensive layout verification, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checks (ERC).
• Collaborate closely with circuit designers to ensure layouts meet quality, performance, and reliability requirements.
• Maintain and manage layout databases using designated Design Management software.
• Engage with the engineering design team to understand design concepts, constraints, and project milestones; accurately and concisely communicate design status and track schedules.
• Proactively and independently identify and resolve design- and PDK-related issues; clearly document and communicate solutions to layout and engineering stakeholders.
• Work closely with Circuit Designers and Mask Layout Designers across global development sites, including the United States, Taiwan, and India.
• Demonstrate strong communication skills and effective teamwork while contributing efficiently within a globally distributed engineering team.

Minimum Qualifications

• Associate’s degree or technical certificate in Computer Science, Mathematics, Electrical Engineering, or a related discipline.
• Foundational understanding of CMOS technology and integrated circuit (IC) design principles.
• Strong attention to detail with the ability to work effectively in a collaborative team environment.

Preferred Qualifications

• Bachelor’s degree in Computer Science, Engineering, or a related field.
• Knowledge of parasitic effects and reliability considerations in advanced IC designs.
• Familiarity with scripting and automation languages, such as SKILL and Python, for layout development and optimization.
• Exposure to advanced semiconductor process technologies, including FinFET and Gate-All-Around (GAA) nodes, is a plus.

Additional Information

Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field.

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