Senior Verification Engineer

Micron Technology; Tlaquepaque; Presencial; MXN 1,115,000 - 1,487,000; Jornada completa

Descripción de la vacante

A leading technology firm is seeking a Senior Verification Engineer in Tlaquepaque, Mexico. The role involves developing verification infrastructure and supporting design engineering teams. Candidates should have a BS in Electrical Engineering or similar, with 3-7 years of experience in CMOS and DRAM design, along with expertise in SystemVerilog methodologies. This full-time position offers an opportunity to innovate in memory and storage solutions.

Formación

• 3-7 years of industry experience.
• Good understanding of ASIC design flow including RTL design and timing analysis.
• Familiarity with DFT verification.

Responsabilidades

• Develop verification infrastructure for DFT testmodes functionality.
• Provide verification support to engineering teams.
• Develop SystemVerilog testbench infrastructure.

Conocimientos

SystemVerilog testbench/UVM

Deep understanding of CMOS

Verification methodology

ASIC design flow

Familiarity with DRAM DFT flow

Educación

BS in Electrical Engineering or Computer Engineering

Descripción del empleo

Senior Verification Engineer

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists developing groundbreaking technologies that transform how the world uses information.

Responsibilities

• Develop verification infrastructure and environment to verify probe and burn DFT testmodes functionality.
• Develop verification infrastructure and environment to port‑over the probe and burn DFT patterns into the verification flow.
• Provide verification support to the DRAM and Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre‑silicon full‑chip and block‑level designs.
• Develop SystemVerilog testbench infrastructure (e.g. UVM/Non‑UVM and Constrained Random Verification Methodology).
• Responsible for test plan execution, running regressions, and code and functional coverage closure.

Minimum Qualifications

• BS in Electrical Engineering, Computer Engineering or equivalent with at least 3‑7 years of industry experience.
• Deep understanding of CMOS and DRAM circuit design and operation.
• Familiarity with SystemVerilog testbench/UVM/Constrained Random verification methodology would be a strong plus.
• Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
• Familiarity with the DRAM DFT flow and DFT verification.

Seniority Level

• Mid‑Senior level

Employment Type

• Full‑time

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail].

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.