Framework Developer Engineer

QUALCOMM, Inc.; Tijuana; Presencial; MXN 900.000 - 1.300.000; Jornada completa

Descripción de la vacante

Qualcomm’s SoC Validation Team seeks a Framework Developer Engineer up to Staff to build and enhance bare‑metal validation frameworks for Snapdragon platforms. You will collaborate with architects, designers and software engineers to enable robust HW validation across Emulation and Post-Si environments.

You will drive new framework features, support diverse core teams, and work on cost-saving validation initiatives while learning new technologies and applying them effectively.

Formación

• 5+ years of hands-on silicon validation and embedded SW development on modern CPU/SoC
• Proficiency with C/C++ coding, and at least familiarity with assembly, VHDL/Verilog and scripting languages such as Python or Perl
• Understanding of mobile chip and/or server architecture (CPU, GPU, DDR, NOCs, Peripherals) and root-cause techniques for low-level issues
• Ability to use lab equipment for testing/validation, including logic analyzers and oscilloscopes
• Debug tools including JTAG and kernel debuggers like Lauterbach Trace32
• Good written and spoken communication skills

Responsabilidades

• Design, develop, debug system/IP validation framework for bare-metal and light-weight RTOS environments
• Understand Snapdragon SoC architecture to enable SVE infrastructure for multiple core teams
• Interface with Design/DV/SW teams to debug issues and enable test infrastructure on Emulation and Post-Si environments
• Enable new framework test flows for MBIST testing in high-volume production screening

Conocimientos

Embedded SW architecture

ARMv8/ARMv9/x86/RISC-V

C/C++ coding

JTAG interfaces

OS/RTOS/Linux kernel internals

Python or Perl

Educación

Bachelor’s degree, Computer and/or Electrical Engineering

Master’s degree, Computer and/or Electrical Engineering

Herramientas

GCC/Clang

Lauterbach Trace32

Python

Descripción del empleo

Company:

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm's SoC Validation Team (SVE – System Validation & Emulation) is part of the central SoC digital hardware organization responsible for the overall quality of the SoC silicon. The validation team works closely with architects, designers, verification engineers, software engineers, and customers to solve the toughest issues spanning board design, SoC RTL, microcontroller firmware, OS/software, and process variation. We are currently seeking a candidate for the position of Framework Developer Engineer up to Staff level title.

In this position you will be developing SVE bare metal framework enabling global teams to effectively validate the Qualcomm HW products. Through close interaction with core teams and understanding their HW validation needs, you will develop solutions to satisfy crucial project milestones on a broad range of the newest Snapdragon SoCs. You will be driving the development of new framework features to e.g. enable ATE testing as part of the production screening process, a new initiative with a major potential for huge cost savings. If you are passionate about resolving tough technical problems, working with various global teams, and intrigued in constantly learning new technologies and applying them efficiently to your work, we’re looking for a candidate just like you!

Responsibilities

• Design, develop, debug system/IP validation framework to be used in bare-metal and light-weight-RTOS environments for various SoC validation activities by global core teams
• Understand the newest Snapdragon SoC architecture and design features, and ensure the SVE infrastructure can support various core teams to achieve planned HW validation goals
• Interface with various IP validation and cross functional teams (Design/DV/SW) to understand and debug complex issues, and to enable the SVE test infrastructure on Emulation and Post-Si environments
• Enable new framework test flows to be used e.g. for MBIST testing in the high-volume production screen flow

Mandatory Skills:

• Good knowledge and understanding of Embedded SW architecture and content development in C/C++ for validation purposes
• Working knowledge of ARMv8/ARMv9/x86/RISC-V CPU architectures, Interrupt handling, Cache coherency, IO Coherency, and SoC architectures with complex SMP/heterogenous cores
• Understanding memory management techniques including weakly ordered memory model, pipelining of memory systems, memory barriers, etc.
• Working knowledge of software build toolchains comprising compilers, Makefiles, linker and scatter files, etc.
• Previous hands‑on SW Boot Loader design and debug experience is highly preferred
• Experience in optimizing code, and efficiently resolving linker issues
• Experience in using JTAG interfaces and debug tools for analyzing HW

Desired Skills

• Exposure to broad range of SoC architecture concepts – interconnects, power management, inter-processor communication techniques, etc.
• Knowledge of Operating systems/RTOS/Linux kernel internals, multithreading, scheduling policies, locking mechanism, Virtual memory, MMU, etc.
• Working knowledge for the use of compilers and linkers such as GCC, CLANG, RVDS, LLVM
• Bring-up of HW-SW solutions on FPGA/emulation platforms and on fresh SOC designs
• Exposure to build automation tools such as Jenkins, and experience in creating automated processes to streamline the development process
• Regression testing exposure: understanding the available methodologies and tools, ability to design, implement and execute comprehensive test suites for SW quality and stability

Minimum Requirements:

• 5+ years of hands‑on silicon validation and embedded SW development experience on modern CPU and SoC architectures
• Proficiency with C/C++ coding, and at least familiarity with assembly, VHDL/Verilog and various scripting languages like Python or Perl
• Understanding of mobile chip and/or server architecture (CPU, GPU, DDR, NOCs, Peripherals, etc.), and systematic debug and root‑cause techniques of low‑level SW/HW issues
• Ability to use lab equipment for testing and validation, including logic analyzers and oscilloscopes
• Debug tools including JTAG and kernel debuggers like Lauterbach Trace32
• Good written and spoken communication skills

Education:

• Required: Bachelor’s, Computer and/or Electrical Engineering
• Preferred: Master’s, Computer and/or Electrical Engineering

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  OR
  Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  OR
  PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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