Attiva gli avvisi di lavoro via e-mail!

Senior Analog IC Design Engineer

IC Resources

Pisa

In loco

EUR 50.000 - 80.000

Tempo pieno

3 giorni fa
Candidati tra i primi

Genera un CV personalizzato in pochi minuti

Ottieni un colloquio e una retribuzione più elevata. Scopri di più

Inizia da zero o importa un CV esistente

Descrizione del lavoro

A leading technology company in Italy is seeking a Senior Analog IC Design Engineering Lead to work on high-speed PLL design and integrated power management for advanced CMOS nodes. This role offers a collaborative environment focused on cutting-edge developments in energy-efficient interconnects and requires proven experience in high-speed designs.

Competenze

  • Proven track record in PLL and power management design, ideally at or near 12nm nodes.
  • Strong background in CMOS analog design fundamentals.
  • Experience in high-speed designs is essential.

Mansioni

  • Design and develop high-speed PLLs (10 GHz and above).
  • Implement on-chip power management circuits such as LDOs and DACs.
  • Collaborate closely with digital, systems, and photonic teams.

Conoscenze

Problem Solving
Detail Oriented
Analog Design Fundamentals

Strumenti

Cadence
Spectre

Descrizione del lavoro

I am recruiting for a Senior Analog IC Design Engineering Lead on behalf of my client, a growing technology company developing next-generation solutions for high-performance data communication. The position is focused on high-speed Phase Locked Loop design and integrated power management within advanced CMOS nodes.

The Senior Analog IC Design Engineering Lead will contribute to cutting-edge developments in energy-efficient interconnects.

Key responsibilities :

  • Design and develop high-speed PLLs (10 GHz and above)
  • Implement on-chip power management circuits such as LDOs and DACs
  • Collaborate closely with digital, systems and photonic teams on complex mixed signal integration
  • Run simulations, oversee layout and verify performance of analog building blocks
  • Bring industry trends and design innovations into the development cycle

Required experience :

  • Proven track record in PLL and power management design, ideally at or near 12nm nodes
  • Strong background in CMOS analog design fundamentals
  • Proficient with tools like Cadence and Spectre
  • Detail oriented with excellent problem solving skills

To be considered for this opportunity, you will need to have experience in high-speed designs.

This is an excellent opportunity for a Senior Analog IC Design Engineer looking to work on novel technologies in a collaborative and forward-looking environment.

Ottieni la revisione del curriculum gratis e riservata.
oppure trascina qui un file PDF, DOC, DOCX, ODT o PAGES di non oltre 5 MB.