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Senior Analog IC Design Engineer

JR Italy

Pavia

Remoto

EUR 50.000 - 90.000

Tempo pieno

3 giorni fa
Candidati tra i primi

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Descrizione del lavoro

A growing technology company is seeking a Senior Analog IC Design Engineer to innovate in high-speed Phase Locked Loop design and integrated power management. This role offers the chance to work on cutting-edge developments in energy-efficient interconnects, collaborating closely with digital and photonic teams. The ideal candidate will have a strong background in CMOS analog design and a proven track record in PLL and power management design. With remote working possibilities, this position is perfect for those looking to contribute to novel technologies in a forward-thinking environment.

Competenze

  • Proven track record in PLL and power management design.
  • Strong background in CMOS analog design fundamentals.

Mansioni

  • Design and develop high-speed PLLs (10 GHz and above).
  • Implement on-chip power management circuits such as LDOs and DACs.

Conoscenze

PLL Design
Power Management Design
CMOS Analog Design
Problem Solving

Strumenti

Cadence
Spectre

Descrizione del lavoro

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I am recruiting for a Senior Analog IC Design Engineer on behalf of my client, a growing technology company developing next-generation solutions for high-performance data communication. The position is focused on high-speed Phase Locked Loop design and integrated power management within advanced CMOS nodes.

The Senior Analog IC Design Engineer will contribute to cutting-edge developments in energy-efficient interconnects.

Key responsibilities:

  • Design and develop high-speed PLLs (10 GHz and above)
  • Implement on-chip power management circuits such as LDOs and DACs
  • Collaborate closely with digital, systems and photonic teams on complex mixed signal integration
  • Run simulations, oversee layout and verify performance of analog building blocks
  • Bring industry trends and design innovations into the development cycle

Required experience:

  • Proven track record in PLL and power management design, ideally at or near 12nm nodes
  • Strong background in CMOS analog design fundamentals
  • Proficient with tools like Cadence and Spectre
  • Detail oriented with excellent problem solving skills

To be considered for this opportunity, you will need to have experience in high-speed designs.

This is an excellent opportunity for a Senior Analog IC Design Engineer looking to work on novel technologies in a collaborative and forward-looking environment.

Remote working may be possible for the right candidate, although Italy is preferred.

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