Senior Analog IC Design Engineer

JR Italy; Napoli; Remoto; EUR 50.000 - 90.000; Tempo pieno

Descrizione del lavoro

An innovative technology company is seeking a Senior Analog IC Design Engineer to lead the design of high-speed Phase Locked Loops and integrated power management solutions. This role offers the chance to work on cutting-edge technologies in a collaborative environment, focusing on energy-efficient interconnects and advanced CMOS nodes. The ideal candidate will have a strong background in analog design and experience with tools like Cadence and Spectre. If you're passionate about pushing the boundaries of technology and thrive in a forward-thinking atmosphere, this opportunity is perfect for you.

Competenze

• Proven track record in PLL and power management design at or near 12nm nodes.
• Strong background in CMOS analog design fundamentals.

Mansioni

• Design and develop high-speed PLLs (10 GHz and above).
• Implement on-chip power management circuits like LDOs and DACs.

Conoscenze

PLL Design

Power Management Design

CMOS Analog Design

Problem-Solving Skills

Strumenti

Cadence

Spectre

Descrizione del lavoro

Job Description

I am recruiting for a Senior Analog IC Design Engineer on behalf of my client, a growing technology company developing next-generation solutions for high-performance data communication. The position focuses on high-speed Phase Locked Loop design and integrated power management within advanced CMOS nodes.

The Senior Analog IC Design Engineer will contribute to cutting-edge developments in energy-efficient interconnects.

Key responsibilities:

• Design and develop high-speed PLLs (10 GHz and above)
• Implement on-chip power management circuits such as LDOs and DACs
• Collaborate closely with digital, systems, and photonic teams on complex mixed-signal integration
• Run simulations, oversee layout, and verify performance of analog building blocks
• Incorporate industry trends and design innovations into the development cycle

Required experience:

• Proven track record in PLL and power management design, ideally at or near 12nm nodes
• Strong background in CMOS analog design fundamentals
• Proficient with tools like Cadence and Spectre
• Detail-oriented with excellent problem-solving skills

To be considered for this opportunity, you should have experience in high-speed designs.

This is an excellent opportunity for a Senior Analog IC Design Engineer interested in working on novel technologies within a collaborative and forward-looking environment.

Remote working may be possible for the right candidate, although Italy is preferred.