Senior Analog IC Design Engineer

JR Italy; Latina; Remoto; EUR 60.000 - 100.000; Tempo pieno

Descrizione del lavoro

An innovative technology company is seeking a Senior Analog IC Design Engineer to lead the design of high-speed Phase Locked Loops and integrated power management solutions. This role involves collaborating with cross-functional teams to develop cutting-edge, energy-efficient technologies. The ideal candidate will have a strong background in CMOS analog design and experience with advanced nodes. This position offers the chance to work on novel projects in a dynamic environment, with the possibility of remote work for the right individual. If you are passionate about analog design and eager to contribute to the future of data communication, this opportunity is for you.

Competenze

• Proven track record in PLL and power management design.
• Strong background in CMOS analog design fundamentals.

Mansioni

• Design and develop high-speed PLLs (10 GHz and above).
• Implement on-chip power management circuits such as LDOs and DACs.

Conoscenze

PLL Design

Power Management Design

CMOS Analog Design

Problem Solving

Strumenti

Cadence

Spectre

Descrizione del lavoro

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Client:

IC Resources

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Other

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EU work permit required:

Yes

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Job Reference:

6895170239646924800337153

Job Views:

1

Posted:

05.05.2025

Expiry Date:

19.06.2025

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Job Description:

I am recruiting for a Senior Analog IC Design Engineer on behalf of my client, a growing technology company developing next-generation solutions for high-performance data communication. The position is focused on high-speed Phase Locked Loop design and integrated power management within advanced CMOS nodes.

The Senior Analog IC Design Engineer will contribute to cutting-edge developments in energy-efficient interconnects.

Key responsibilities:

• Design and develop high-speed PLLs (10 GHz and above)
• Implement on-chip power management circuits such as LDOs and DACs
• Collaborate closely with digital, systems and photonic teams on complex mixed signal integration
• Run simulations, oversee layout and verify performance of analog building blocks
• Bring industry trends and design innovations into the development cycle

Required experience:

• Proven track record in PLL and power management design, ideally at or near 12nm nodes
• Strong background in CMOS analog design fundamentals
• Proficient with tools like Cadence and Spectre
• Detail oriented with excellent problem solving skills

To be considered for this opportunity, you will need to have experience in high-speed designs.

This is an excellent opportunity for a Senior Analog IC Design Engineer looking to work on novel technologies in a collaborative and forward-looking environment.

Remote working may be possible for the right candidate, although Italy is preferred.