Senior Ams Verification Leader

NXP Semiconductors NV; Bardi; In loco; EUR 120.000 - 150.000; Tempo pieno

Vantaggi offerti da questo lavoro

annual incentive opportunities

equity

competitive benefits package

Descrizione del lavoro

NXP Semiconductors NV is seeking a Senior AMS Verification leader to drive the verification strategy for automotive and industrial ASIC/mixed-signal projects. You will own AMS verification deliverables from specification to silicon correlation and mentor engineers to ensure robust, high-quality silicon.

Collaborate with global experts and shape verification practices at scale. The role emphasizes hand-on verification, testbench development, and cross-domain collaboration across RTL, analog, and

Competenze

• 10+ years of experience in AMS or mixed-signal IC verification.
• Strong experience leading verification activities for complex ASIC or mixed-signal IC projects.
• Solid knowledge of analog fundamentals, digital RTL debug, co-simulation, and mixed-signal verification methodologies.
• Hands-on experience with verification plans, testbenches, regressions, coverage, reviews, and bug closure.
• Experience with Verilog, SystemVerilog, UVM, SVA, Verilog-AMS, SystemC, WREAL/RNM modelling.
• Experience with EDA tools such as Cadence Virtuoso, Xcelium, Spectre, and vManager.
• Good scripting skills in Python, Perl, or TCL, and experience with Git, SVN, or DesignSync.
• AMS/mixed-signal verification.

Mansioni

• Lead AMS verification activities and guide engineers toward successful project delivery.
• Define verification plans, strategies, environments, regressions, and coverage objectives.
• Develop and validate mixed-signal simulation environments, models, checkers, and reusable components.
• Bridge digital and mixed-signal verification flows for robust top-level verification.
• Drive methodology improvements to increase simulation efficiency, reuse, quality, and cost effectiveness.
• Support design reviews, bug tracking, post-silicon correlation, and continuous improvement across projects.
• Own key AMS verification deliverables from specification review to silicon correlation.

Conoscenze

AMS verification

Mixed-signal IC verification

Verilog

SystemVerilog

UVM

SVA

Verilog-AMS

SystemC

WREAL/RNM modelling

Python scripting

RTL debug

Co-simulation

Bug closure

Verification plans

Strumenti

Cadence Virtuoso

Xcelium

Spectre

vManager

Descrizione del lavoro

In this role you lead mixed-signal verification efforts for automotive and industrial products within NXP's Advanced Power System team. You'll define verification strategies, drive methodology improvements, and collaborate with global experts to deliver robust silicon with strong quality. You will own AMS verification deliverables from specification to silicon correlation and bridge digital and analog verification flows. This position offers impact across complex ASIC/mixed-signal projects and opportunities to shape verification practices at scale.

• annual incentive opportunities
• equity
• competitive benefits package
• Lead AMS verification activities and guide engineers toward successful project delivery
• Define verification plans, strategies, environments, regressions, and coverage objectives
• Develop and validate mixed-signal simulation environments, models, checkers, and reusable components
• Bridge digital and mixed-signal verification flows for robust top-level verification
• Drive methodology improvements to increase simulation efficiency, reuse, quality, and cost effectiveness
• Support design reviews, bug tracking, post-silicon correlation, and continuous improvement across projects
• Own key AMS verification deliverables from specification review to silicon correlation
• 10+ years of experience in AMS or mixed-signal IC verification
• Strong experience leading verification activities for complex ASIC or mixed-signal IC projects
• Solid knowledge of analog fundamentals, digital RTL debug, co-simulation, and mixed-signal verification methodologies
• Hands-on experience with verification plans, testbenches, regressions, coverage, reviews, and bug closure
• Experience with Verilog, SystemVerilog, UVM, SVA, Verilog-AMS, SystemC, WREAL/RNM modelling
• Experience with EDA tools such as Cadence Virtuoso, Xcelium, Spectre, and vManager
• Good scripting skills in Python, Perl, or TCL, and experience with Git, SVN, or DesignSync
• Analytical mindset
• Strong ownership
• Structured problem-solving
• AMS/mixed-signal verification

Senior AMS Verification leader pavia, lombardia, it