R&D – Head of Embedded NVM Technologies

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R&D – Head of Embedded NVM Technologies, Pavia

Client: Theron Solutions

Location:

Job Category: Other

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EU work permit required: Yes

Job Reference:

4287033516446711808337139

Job Views:

2

Posted:

26.04.2025

Expiry Date:

10.06.2025

Job Description:

Note: THIS ROLE REQUIRES A RELOCATION TO DHOLERA, INDIA once the FAB is built.

Responsibilities:

1. Integration responsibilities to add eNVM (embedded Non-Volatile Memory) features to 28 110nm platform technologies, including MTP and Flash. Collaborate with IP providers as needed.
2. Design and layout of test chips to aid in device/technology optimization, reliability assessment, and SPICE model extraction.
3. Manage projects end-to-end, from initial justification to qualification and yield ramp, ensuring performance, quality, schedule, and cost targets are met.
4. Build and lead a cross-functional team across diverse geographies.
5. Develop strong customer relationships based on confidence in the company's technical capabilities.
6. Conduct competitor benchmarking; own the technology roadmap.
7. Present to internal and customer senior executives.
8. Potential involvement in OTP development.
9. Travel requirements: a few weeks per quarter.

Candidate qualities:

• Ability to manage, mentor, and lead a team of highly motivated professionals.
• Self-motivated, capable of working independently with a strong drive to succeed.
• Team player, capable of working across diverse cross-functional teams worldwide.
• Leadership skills to influence all organizational levels.
• Inclusive, adaptable to various global norms.
• Curious, resilient, data-driven problem solver.
• Collaborative, relationship-builder, supportive, open-minded.
• Innovative, proactive in exploring new ideas and adapting quickly to change.

Qualifications:

1. M.S. or PhD in Electrical Engineering, Materials Science, or related field.
2. Strong understanding of CMOS and eNVM device physics, process modules, yield improvement, failure mechanisms, and analytical techniques.
3. Deep knowledge of key eNVM technologies (charge trap, floating gate, RRAM, MRAM, etc.).
4. Understanding of technology parameters and figures of merit (bit cell size, macro size, endurance, retention, power, latency, mask count, etc.); experience in achieving competitive performance.
5. Proven track record of delivering these technologies into volume manufacturing.
6. Ability to lead cross-functional teams to meet project timelines and budgets.
7. Experience working across different cultures and geographies.
8. Good team player with an innovative and competitive mindset.

Desired Experience Level:

1. 15+ years in the semiconductor industry.
2. Successful track record of developing new technologies into high-volume production.
3. Strong problem-solving skills using design of experiments and analytical tools.

EOE: Our client is an Equal Opportunity Employer committed to a work environment free of discrimination and harassment. Employment decisions are based on business needs, job requirements, and individual qualifications, without regard to race, color, religion, sex, age, disability, sexual orientation, gender identity, or other protected characteristics.