MEMS ASIC Digital Verification Engineer - Impact & Growth

STMicroelectronics Italia; Agrate Brianza; On-site; EUR 40,000 - 45,000; Full time

Job summary

STMicroelectronics Italia seeks a Digital Verification engineer with hands-on ASIC verification experience. You will join the MEMSs GROUP and contribute across the verification lifecycle from specification to industrialization.

You will define and develop verification testbenches, create verification components, and craft test cases for simulation. Strong knowledge of SystemVerilog, UVM, and scripting languages is required; English fluency and teamwork are essential.

Qualifications

• 3–5 years of experience in digital verification.
• Experience with verification testbenches and UVM.
• Knowledge of SystemVerilog and Python scripting.
• Familiarity with I2C/SPI/I3C protocols is a plus.

Responsibilities

• Define and develop verification testbenches and components.
• Develop DSP models and digital control logic; create simulation cases and debug failures.

Skills

UVM

SystemVerilog

Python

TCL

Testbench

I2C/SPI/I3C

English

Tools

Verilog simulators

Version control

Job description

STMicroelectronics Italia seeks a Digital Verification engineer with hands-on ASIC verification experience. You will join the MEMSs GROUP and contribute across the verification lifecycle from specification to industrialization.

You will define and develop verification testbenches, create verification components, and craft test cases for simulation. Strong knowledge of SystemVerilog, UVM, and scripting languages is required; English fluency and teamwork are essential.