Lead Digital Design Engineer – Power Management Innovation

Renesas Electronics Corporation; Catania; In loco; EUR 61.000 - 82.000; Tempo pieno

Vantaggi offerti da questo lavoro

Bonus eligible

Competitive benefits

Descrizione del lavoro

Renesas Electronics Corporation in Sicily, Italy, seeks a Snr Staff Digital Design Engineer with a BSc/MSc in EE/ECE and 8–12 years of industry experience to lead digital design for advanced digital power management ICs.

You will debug, verify, and automate design flows, mentoring junior engineers and shaping design blocks in pre- and post-silicon contexts. A permanent role with a strong toolchain and competitive package awaits.

Competenze

• BSc/MSc in Electrical Engineering/Computer Engineering (EE/ECE).
• 8–12 years of relevant industry experience.
• Proficient in Verilog-based CDC/RDC/LINT clean designs.
• Comfortable debugging mixed-signal designs with SystemVerilog testbenches.
• Experience with standard serial interfaces (I2C, I3C, SPI, I2S).
• Strong analytical and debugging methodologies.
• Excellent written and verbal communication skills.
• Experience with Cadence or Synopsys tool flows.

Mansioni

• Develop, debug, and verify digital designs in pre- and post-silicon environments.
• Write tests to verify bulk design intent per specification.
• Develop and improve design automation scripts.
• Manage assigned design blocks in requirements, architecture, and implementation.
• Research and present new tools to aid design development.

Conoscenze

Verilog

SystemVerilog

Gate-level debug

I2C/I3C/SPI/I2S

Analytical skills

Communication skills

Cadence/Synopsys

Technical leadership

Formazione

BSc/MSc in EE/ECE

Strumenti

Cadence

Synopsys

Verilog

SystemVerilog

Descrizione del lavoro

Renesas Electronics Corporation in Sicily, Italy, seeks a Snr Staff Digital Design Engineer with a BSc/MSc in EE/ECE and 8–12 years of industry experience to lead digital design for advanced digital power management ICs.

You will debug, verify, and automate design flows, mentoring junior engineers and shaping design blocks in pre- and post-silicon contexts. A permanent role with a strong toolchain and competitive package awaits.