End-host stacks for datacenter class applications - 2026_CDR_DEIB_11

Italian Ministry of Education, University and Research; Italia; On-site; EUR 42,000 - 55,000; Full time

Job summary

Politecnico di Milano seeks a researcher to investigate novel system architectures for accelerating the network stack of data-center-class applications. The work will focus on the co-design of operating-system mechanisms, networking software, and programmable hardware accelerators to improve the performance and efficiency of high-throughput, data-intensive workloads.

The candidate will explore hardware-software interaction, including data movement, communication, synchronization, and dynamic

Qualifications

• Quality, originality, and innovation of the research proposal, with reference to the research program covered by this selection (up to 10 points)
• Relevance and significance of previous research activities and professional experience in relation to the research program (up to 30 points)
• Relevance and significance of submitted publications with respect to the research program (up to 30 points)
• Interview, aimed at assessing the candidate’s research aptitude, their ability to implement the proposed project, and their knowledge of English and/or other relevant languages for the research (up to 30 points)

Job description

Organisation/Company Politecnico di Milano Research Field Engineering Researcher Profile Recognised Researcher (R2) Leading Researcher (R4) First Stage Researcher (R1) Established Researcher (R3) Application Deadline 20 Nov 2026 - 12:00 (UTC) Country Italy Type of Contract To be defined Job Status Not Applicable Is the job funded through the EU Research Framework Programme? Horizon 2020 Is the Job related to staff position within a Research Infrastructure? No

Offer Description

The research activity will investigate novel system architectures for accelerating the network stack of data-center-class applications. The work will focus on the co-design of operating-system mechanisms, networking software, and programmable hardware accelerators to improve the performance and efficiency of high-throughput, data-intensive workloads. A key objective will be to identify network-processing functions that can benefit from hardware acceleration while retaining flexibility and programmability. The research will explore extensions to operating systems and networking stacks that enable applications to exploit hardware acceleration capabilities available in novel NIC architectures. Particular attention will be devoted to hardware-software interaction, including mechanisms for data movement, communication, synchronization, and dynamic allocation of processing between the host and the NIC.

Quality, originality, and innovation of the research proposal, with reference to the research program covered by this selection (up to 10 points)

Relevance and significance of previous research activities and professional experience in relation to the research program (up to 30 points)

Relevance and significance of submitted publications with respect to the research program (up to 30 points)

Interview, aimed at assessing the candidate’s research aptitude, their ability to implement the proposed project, and their knowledge of English and/or other relevant languages for the research (up to 30 points)

• EUROPE

Eligibility of fellows: country/ies of residence:

• All

Eligibility of fellows: nationality/ies: