Early Careers Digital Design Engineer

Apple Inc.; Livorno; In loco; EUR 40.000 - 70.000; Tempo pieno

Descrizione del lavoro

Join a leading technology company as a digital design engineer, working through all phases of product development. Your role will involve designing and qualifying RTL code while collaborating to tackle challenging problems, all within a dynamic and innovative environment.

Competenze

• Proficient with RTL coding in Verilog, SystemVerilog or VHDL.
• Knowledge of digital frontend flows required.
• Fluent in English (written and verbal).

Mansioni

• Define features and interfaces for digital IPs.
• Implement in SystemVerilog and qualify RTL code.
• Ensure energy efficiency and area constraints.

Conoscenze

RTL structures and coding

Digital frontend flows

Analytical skills

Problem solving

Interpersonal skills

Strumenti

SystemVerilog

Verilog

VHDL

Scripting languages

Descrizione del lavoro

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Multifaceted, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! Do you love working on challenges that no one has solved yet? At Apple, we are pushing the boundary of what is possible to improve the lives of our customers.

Description

As part of our digital design team you will get involved in all phases of the product development cycle. You will work with chip and system architects to understand the top level requirements of our digital functions and develop detailed specifications. A key part of your daily work is the definition of features and interfaces to control analog and digital IPs, the implementation in SystemVerilog and the flows to qualify RTL code. You will also need to provide constraints, oversee synthesis and power reports, root-cause and resolve timing and power issues and ensure maximal QoR throughout your design.Your designs will need to balance energy efficiency and area constraints with project schedule and maintainability. We are looking for a team player who takes over new challenges to find solutions in collaboration with our highly motivated digital and analog design teams.

Minimum Qualifications

• Proficient with RTL structures and coding in Verilog, SystemVerilog or VHDL
• Knowledge of digital frontend flows and methodologies
• Excellent interpersonal skills and well-organised working style
• Strong analytical and problem solving skills
• Fluent English language skills are required (written and verbal)

Preferred Qualifications

• Awareness of asynchronous design concepts, related rules and restrictions
• Scripting language knowledge (perl, python or similar)