Design Verification Intern — AMS & SystemVerilog

Analog Devices, Inc.; Assago; On-site; EUR 10,000 - 12,000; Full time

Job summary

Analog Devices, Inc. in Milan, Italy offers an internship in their High-Performance Power Group, focusing on Analog Mixed Signal Design Verification.

You will learn through hands-on projects within a team of experts, contributing to verification planning, modeling, and simulations. The program emphasizes learning, professional development, and potential pathways to full-time roles, with exposure to Verilog-AMS, SystemVerilog, and UVM environments, and the chance to pursue a Master Thesis in

Qualifications

• Pursuing master's in Electrical Engineering or related field.
• Possibility of Master Thesis in Analog Mixed Signal Design Verification.
• Internship in Milan focusing on mixed-signal verification workflows.

Responsibilities

• Assist in design verification of analog/mixed-signal circuits.
• Contribute to verification plans and stimulus generation.
• Work with SystemVerilog and Verilog-AMS based testbenches and AMS simulations.

Skills

Analog/Mixed-Signal design

Verilog AMS

SystemVerilog

Verification planning

UVM

Education

Pursuing Master’s degree in Electrical Engineering

Tools

Verilog AMS

SystemVerilog

UVM

Job description

Analog Devices, Inc. in Milan, Italy offers an internship in their High-Performance Power Group, focusing on Analog Mixed Signal Design Verification.

You will learn through hands-on projects within a team of experts, contributing to verification planning, modeling, and simulations. The program emphasizes learning, professional development, and potential pathways to full-time roles, with exposure to Verilog-AMS, SystemVerilog, and UVM environments, and the chance to pursue a Master Thesis in